Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model inference—alongside processor cores and memory subsystems using System Verilog.
The base salary range is $135,000 - $170,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.
- Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model inference—alongside processor cores and memory subsystems using System Verilog
- Logic design, implementation, and verification using Verilog, System Verilog, and any required programming and scripting languages
- Synthesize and optimize RTL for timing, area, and power
- Explore micro-architecture and architectural tradeoffs via quick modelling using scripting languages such as python, Perl etc
- Developing unit level test environments and test cases
- Master’s degree in electrical/Electronics/Computer Engineering
- new-hire RSU grants
- annual RSU grants
- highly competitive benefits
