A recognized technical leader who thinks in systems, not individual IP blocks, defining technical strategy and leading engineering transformation across organizational boundaries to build the next generation of subsystem interoperability verification.
Compensation
Your recruiter will provide more details about the salary range and benefits during the hiring process.
Responsibilities
Define the technical vision for subsystem interoperability spanning Controller, PHY, firmware, VIP, verification environments, and customer configurations across multiple high-speed interface IP families
Architect a scalable Interop Verification Platform that enables continuous integration, verification, and qualification across IP releases
Establish reusable verification architectures, methodologies and golden reference environments covering functional verification, protocol compliance, error and stress scenarios, coverage, assertions, CDC/RDC and system initialization
Lead the most complex cross-IP technical investigations and drive systemic solutions across RTL, PHY, firmware, VIP, testbench and implementation boundaries when interoperability issues surface
Partner with Controller and PHY architects and R&D teams to influence interfaces, observability, design-for-verification and subsystem architecture early in the development lifecycle
Requirements
Nice to have: CDC/RDC
Nice to have: formal verification
Nice to have: emulation/prototyping
Nice to have: CI/CD
Nice to have: distributed verification infrastructure
An adaptive, self-motivative design verification engineer to join the Verification Engineering team, focusing on verification of complex Analog/Mixed-Signal IPs targeted for integration into AMD SoCs.
Responsibilities
Develop/Maintain tests for functional verification and performance verification at the core level
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Develop feature-level verification plans and verify IP across RTL, gate-level simulation, and Analog/Mixed-Signal simulation
Develop SystemVerilog/UVM-based testbenches, components, sequences, and verification infrastructure
Requirements
Bachelors or Masters degree in computer engineering/Electrical Engineering
Contribute towards bug free first-time pass silicon (Chip), understanding architecture and design of IP to make sure IP use cases are clear and IP is verified correctly with no bugs.
Plan and develop test-benches using standard methodology using different Hardware Description language (HDL).
Run simulation using industry leading tools like Synopsys VCS and Cadence Incisive.
Develop testcases in HDL for exercising scenarios.
Identify and close various functional and code coverage scenarios to achieve 100% code and functional coverage goal.
Requirements
Master’s degree in Electrical Engineering or related field
Design and implement ASIC/FPGA verification environments using UVM & SystemVerilog, develop testbenches, coverage models, and collaborate with cross‑functional teams.
Locations (2)
El Segundo, California, United States
Huntington Beach, California, United States
Compensation
Summary pay range for Associate (Leve 2): $85,850 - $116,150
Summary pay range for Experienced (Level 3) $104,550 - $141,450
Summary pay range for Lead (Level 4): $126,650 - $171.350
Responsibilities
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
Develop self‑checking and reusable test benches from the ground up.
Create Functional Coverage Models and conduct Code Coverage analysis.
Set up regression tests and collect coverage metrics.
Assist in FPGA‑based prototyping and validation.
Requirements
Bachelor of Science in Engineering (Electrical, Mechanical, or Aeronautical)
Lead technical design and development of full stack enterprise SaaS applications in a global engineering team.
Responsibilities
Design, develop, test, and maintain full stack enterprise SaaS applications using Java, Spring/Spring Boot, REST APIs, Angular, JavaScript/TypeScript, and SQL Server/Oracle.
Lead technical design, code reviews, implementation approach, and engineering standards within the development team.
Build, test, and deliver complex frameworks, services, UI components, and application features while diagnosing and resolving complex product issues.
Drive clean code, reusable design, SOLID principles, design patterns, secure coding, automated unit testing, and maintainable architecture.
Ensure code quality and compliance using tools and practices such as Sonar, Dependency Track, peer reviews, unit testing, and code coverage guidelines.
Requirements
Bachelor’s degree in Computer Science, Software Engineering, or a related field, or equivalent practical experience.
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