- Yokneam, Israel
- 0+ years
Design‑for‑Test Engineer on NVIDIA’s ATPG team
Responsibilities
- Take part in state of the art Design for Test/ATPG flows and implementation
- Take part in ATPG ownership on a project, from Arch & planning to pattern generation, verification and post‑silicon bring up and diagnosis
- Invent and maintain automation flows that provide the short test time to production
Requirements
- BSc. in Electrical Engineering or Computer Engineering
- Nice to have: knowledge of DFT including scan, BIST, on‑chip scan compression, fault models, ATPG, and fault simulation
- Nice to have: Experience in Mentor TestKompress ATPG tool and retargeting flow
- Nice to have: Experience with ATE and Silicon bring‑up