- Santa Clara, California, United States
- $206K–$251K per year
- 3+ years
Compensation
Base Pay Range $205,740.00-$251,460.00
Responsibilities
- Work with the architecture team to understand and define power management requirements.
- Architect, design and implement core clocking, reset and power management solutions.
- Microarchitecture development and specification. Ensure that knowledge is shared via clear documentation and participation in a culture of collaborative design.
- Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
- Work with a physical implementation team to implement and optimise physical design to meet frequency, area, power goals.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related technical discipline
- Nice to have: Dynamic voltage and frequency scaling (DVFS)
- Nice to have: Di/dt mitigation strategies
- Nice to have: DFT
- Nice to have: MBIST