Work with the architecture team to understand and define power management requirements.
Architect, design and implement core clocking, reset and power management solutions.
Microarchitecture development and specification. Ensure that knowledge is shared via clear documentation and participation in a culture of collaborative design.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with a physical implementation team to implement and optimise physical design to meet frequency, area, power goals.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related technical discipline
Nice to have: Dynamic voltage and frequency scaling (DVFS)
Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
Requirements
BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.