- Santa Clara, California, United States
- Full-time · Senior
- $114K–$171K per year
- 5+ years
Staff DFT engineer responsible for developing and implementing DFT methodologies and flows for advanced ASICs in the ODSP program.
Compensation
Expected Base Pay Range (USD) 113,920 - 170,600, $ per annum
Responsibilities
- Implement scan, compression, OCC, wrappers and MBIST on assigned blocks/partitions.
- Run ATPG, analyze coverage, and drive coverage improvement (test points, fault exclusions).
- Run DFT DRC, gate-level (zero-delay and SDF) simulations, and debug failures.
- Support DFT timing constraints and closure with PD/STA teams.
- Generate patterns and support silicon bring-up and ATE pattern debug.
Requirements
- BS/MS in EE/CE