Design, implement, and validate FPGA‑based DSP systems on embedded platforms, collaborating with cross‑functional teams and optimizing for performance and resource efficiency.
Compensation
The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD).
Responsibilities
Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains
Develop and optimize DSP algorithms for high‑throughput hardware blocks
Collaborate with cross‑functional teams to integrate FPGA designs with software and firmware
Test, verify, and validate FPGA designs for functional correctness and performance
Optimize designs for timing, area, power, and throughput
Requirements
Bachelor’s degree in Electrical Engineering or Computer Engineering
Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains; develop and optimize DSP algorithms; collaborate with cross‑functional teams; test, verify, and validate FPGA designs; optimize designs for timing, area, power, and throughput; develop reusable hardware IP blocks; maintain documentation; contribute to innovation.
Compensation
Salary at Booz Allen is determined by various factors, including but not limited to location, the individual’s particular combination of education, knowledge, skills, competencies, and experience, as well as contract-specific affordability and organizational requirements. The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD).
Responsibilities
Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains.
Develop and optimize DSP algorithms including filtering, detection, synchronization, modulation and demodulation, transforms into high‑throughput, resource‑efficient hardware blocks.
Collaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures.
Test, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints.
Optimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows.
Requirements
Bachelor’s degree in an Electrical Engineering or Computer Engineering field
Nice to have: Experience implementing or prototyping DSP algorithms in hardware
Nice to have: Experience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation
Nice to have: Experience with porting and adapting vendor RF transceiver reference designs such as RTL, IP cores, and drivers to FPGA evaluation boards and custom platforms
