Seeking an RTL Design Engineer to join the Neural Network Engine (NNE) design team to define microarchitecture and deliver production-quality RTL for compute, memory, datapath, and control blocks in an advanced SoC environment.
Compensation
The listed base salary range for this role is $237,000 - $296,000 for San Francisco Area based applicants.
Design, implement, and validate FPGA‑based DSP systems on embedded platforms, collaborating with cross‑functional teams and optimizing for performance and resource efficiency.
Compensation
The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD).
Responsibilities
Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains
Develop and optimize DSP algorithms for high‑throughput hardware blocks
Collaborate with cross‑functional teams to integrate FPGA designs with software and firmware
Test, verify, and validate FPGA designs for functional correctness and performance
Optimize designs for timing, area, power, and throughput
Requirements
Bachelor’s degree in Electrical Engineering or Computer Engineering
The Cleared Recruiter is responsible for delivering full lifecycle recruiting support across a portfolio of cleared positions ranging from Secret to CI Poly, focusing on SOCOM contracts.
Responsibilities
Execute full lifecycle recruiting for cleared positions, including sourcing, screening, assessing, and guiding candidates through the hiring process.
Verify candidate clearance information and collaborate with Personnel Security to ensure accuracy, compliance, and timely coordination.
Conduct proactive outreach and build pipelines for high-demand cleared skillsets, ensuring consistent engagement with passive and active candidates.
Provide thorough candidate preparation for customer interviews, including briefing on role expectations and navigating sensitive clearance-related discussions appropriately.
Maintain accurate and detailed records within the ATS (iCIMS), including candidate profiles, screening notes, disposition details, and compliance documentation.
Requirements
Bachelor’s degree preferred
Nice to have: iCIMS ATS
Nice to have: Pipelining tools (CXM)
Nice to have: Previous recruiting work with SOCOM contracts
Lead insights and media research projects for Apple’s advertising products across EMEA, partnering with Marketing and Sales teams to deliver compelling insights and develop analytical tools and research studies.
Responsibilities
Lead insights and media research projects for Apple’s advertising products across EMEA
Partner with Marketing and Sales teams to deliver compelling insights
Collaborate with data scientists, analysts, and researchers to develop best-in-class analytical tools, data products, and research studies
Lead project activities and mentor less experienced engineers; architect, specify, implement, simulate, and benchmark MCU and DSP systems and hardware accelerators; contribute to design methodology and flow improvements; consult product integration teams; participate in verification and FPGA prototyping; coordinate SDK development with software team.
Responsibilities
Lead project activities and mentor less experienced engineers
Architect, specify, implement, simulate, and benchmark MCU and DSP systems as well as hardware accelerators
Contribute to design methodology and design flow improvements
Consult the product integration teams in the definition, the integration and use of these systems
Participate to the verification and FPGA prototyping of these systems
Requirements
Minimum BS/MS in Electrical Engineering or a related technical field
Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains; develop and optimize DSP algorithms; collaborate with cross‑functional teams; test, verify, and validate FPGA designs; optimize designs for timing, area, power, and throughput; develop reusable hardware IP blocks; maintain documentation; contribute to innovation.
Compensation
Salary at Booz Allen is determined by various factors, including but not limited to location, the individual’s particular combination of education, knowledge, skills, competencies, and experience, as well as contract-specific affordability and organizational requirements. The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD).
Responsibilities
Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains.
Develop and optimize DSP algorithms including filtering, detection, synchronization, modulation and demodulation, transforms into high‑throughput, resource‑efficient hardware blocks.
Collaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures.
Test, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints.
Optimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows.
Requirements
Bachelor’s degree in an Electrical Engineering or Computer Engineering field
Nice to have: Experience implementing or prototyping DSP algorithms in hardware
Perform and interpret laboratory tests at all complexity levels, maintain quality control, and support patient care at Cleveland Clinic Main Campus.
Compensation
This role is eligible for a sign-on bonus of up to $5,000
Responsibilities
Follow laboratory procedures for specimen handling and processing, test analyses, reporting and maintaining records of patient test results.
Maintain regulatory knowledge and awareness as it pertains to specific job duties.
Adhere to the laboratory’s quality control policies, document all quality control activities, instrument and procedural calibrations and maintenance performed.
Assume responsibility for and take action regarding any quality control or quality assurance issues as it pertains to specific job duties.
Maintain instruments and equipment in accordance with manufacturer’s specifications.
Requirements
Bachelor's degree in a chemical, biological, clinical or medical laboratory science, or medical technology from an accredited institution
Nice to have: Certification as a Medical Technologist (MT, MLT or MLS) or certification eligible from ASCP or AMT
Nice to have: Experience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation
Nice to have: Experience with porting and adapting vendor RF transceiver reference designs such as RTL, IP cores, and drivers to FPGA evaluation boards and custom platforms
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