Referso Jobs

Senior Signal and Power Integrity Engineer

Cisco · Posted Nov 6, 2026

Open

Bangalore, India
Senior
7+ years

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Senior Signal and Power Integrity Engineer

Cisco · Posted Nov 6, 2026

Open

Bangalore, India
Senior
7+ years

Apply with Referso

Signal and Power Integrity Technical Leader

Cisco · Posted Nov 6, 2026

Open

Bangalore, India
10+ years

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Lead signal and power integrity design and analysis for high-speed interconnects and power distribution networks in Cisco’s Network Hardware Engineering team.

Responsibilities

Model and simulate high-speed links, including high-speed I/O, IC package, and system interconnections
Model and analyze power delivery networks
Electromagnetic modeling of complex 3D structures
Perform pre- and post-route signal integrity analysis of PCB and ASIC package designs
Write signal integrity design guidelines, test plans, and test reports

Requirements

Bachelor’s Degree in BSEE
Master’s Degree in Electrical Engineering
Nice to have: high-speed NRZ
Nice to have: PAM4 SerDes
Nice to have: high-speed PCB/package development

Skills

simulation of transmission lines channel modeling signal/power integrity analysis VNA TDR oscilloscopes

ASIC Packaging SI/PI Engineer

Cisco · Posted Nov 6, 2026

Open

San Jose, California, United States
Hybrid
Full-time · Mid
$126K–$177K per year
2+ years

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Signal and Power Integrity Engineer to develop next generation ASIC packaging, design rules, and validate high-speed interconnects.

Compensation

The starting salary range posted for this position is $125,700.00 to $176,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling
Analyze substrate signal integrity and power integrity
Design, document, and develop ASIC packages
Collaborate with system partners, vendors, and design leads

Requirements

Bachelor's degree
Master's degree
Nice to have: High-Bandwidth Memory
Nice to have: HBM
Nice to have: Die-to-die interfaces

Skills

Signal Integrity Power Integrity High-Speed Design Transmission Line Theory Electromagnetics Scattering Parameters

ASIC Packaging SI/PI Engineer (Hybrid)

Cisco · Posted Nov 6, 2026

Open

San Jose, California, United States
Hybrid
Full-time · Mid
$126K–$177K per year
2+ years

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Seeking a qualified Signal and Power Integrity Engineer to help develop next-generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.

Compensation

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Perform SI/PI characterization, validation, and debug of high-speed systems and packages.

Requirements

Bachelors
Masters
Nice to have: High-bandwidth memory (HBM)
Nice to have: High-speed memory interface SI
Nice to have: Die-to-die interfaces (UCIe)

Skills

Senior Signal and Power Integrity Engineer

Cisco · Posted Nov 6, 2026

Open

Bangalore, India
Full-time · Senior
7+ years

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Lead signal and power integrity engineering for high‑speed systems in Cisco’s Network Hardware Engineering team.

Responsibilities

Deliver system‑level signal and power integrity solutions for high‑speed boards and packages
Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports
Improve and optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations
Design and characterize test structures and channel models for Serdes and interconnects
Collaborate with multi‑functional teams – HW, PCB Layout, SW, MFG, ASIC

Requirements

Bachelor's or Master’s Degree in Electrical Engineering

Skills

Signal and Power Integrity Hardware design Lab measurements EM and transmission line concepts Timing, jitter, crosstalk, noise Channel modeling

Signal and Power Integrity Technical Leader

Cisco · Posted Nov 6, 2026

Open

Bangalore, India
Full-time · Manager
10+ years

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Lead signal and power integrity design and analysis for high-speed interconnects and power distribution networks in Cisco’s next-generation networking products.

Responsibilities

Model and simulate high-speed links and power delivery networks
Electromagnetic modeling of complex 3D structures
Perform pre- and post-route signal integrity analysis of PCB and ASIC package designs
Write signal integrity design guidelines, test plans, and reports
Decide PCB material and stack-up, work with vendors on DFM issues

Requirements

Bachelor’s Degree in BSEE
Master’s Degree in Electrical Engineering
Nice to have: Master's or PhD in Electrical Engineering
Nice to have: Knowledge of optical transceiver module types

Skills

Signal Integrity Power Integrity High-speed interconnects Power distribution networks EM theory Transmission line modeling

Signal and Power Integrity Engineer

Cisco · Posted Nov 5, 2026

Open

Bangalore, India
4+ years

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Responsible for delivering system-level signal and power integrity solutions for high-speed systems, boards and packages, developing SI rules, reviewing design implementation, building test plans, and documenting characterization and measurement reports.

Responsibilities

Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports.
Improve & optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations for high-speed designs.
Design & characterize test structures & channel models to correlate simulations with measurements for Serdes and interconnects.
Collaborate with multi-functional teams - HW, PCB Layout, SW, MFG, ASIC.
Be responsible for electrical characterization and verification of Transmitter/Receiver SERDES settings to meet industry standards and internal Cisco requirements.

Requirements

Bachelor's or Master’s Degree in Electrical Engineering

Skills

hardware design Signal and Power Integrity lab measurements real-time scope

Signal and Power Integrity Engineer

Cisco · Posted Nov 5, 2026

Open

Bangalore, Karnataka, India
On-site
Full-time · Mid
4–7 years

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Delivering system-level signal and power integrity solutions for large sophisticated high-speed systems, boards & packages.

Responsibilities

Deliver system-level signal and power integrity solutions for large sophisticated high-speed systems, boards & packages.
Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports.
Improve & optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations for high-speed designs.
Design & characterize test structures & channel models to correlate simulations with measurements for Serdes and interconnects.
Collaborate with multi-functional teams - HW, PCB Layout, SW, MFG, ASIC.

Requirements

Bachelor's Degree in Electrical Engineering
Master’s Degree in Electrical Engineering
Nice to have: 56G PAM4
Nice to have: 25G NRZ Serdes
Nice to have: 10G NRZ Serdes

Skills

Signal and Power Integrity Hardware design Real-time scope Sampling scope

Senior Signal and Power Integrity Engineer

Senior Signal and Power Integrity Engineer

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Signal and Power Integrity Technical Leader

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ASIC Packaging SI/PI Engineer

Compensation

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ASIC Packaging SI/PI Engineer (Hybrid)

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Senior Signal and Power Integrity Engineer

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Signal and Power Integrity Technical Leader

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Signal and Power Integrity Engineer

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Signal and Power Integrity Engineer

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Channel Modeling jobs

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