Lead the interface between foundry partners and Micron design teams to advance HBM DRAM technology.
Compensation
$150,000.00 - $308,000.00 a year
Responsibilities
Act as the primary technical interface between foundry partners and Micron design organizations
Drive closure of design-process gaps through collaborative engagement with foundry process teams
Influence foundry roadmaps related to TSV, BEOL, reliability, and design enablement
Define technology requirements for future HBM and custom memory products
Perform HSPICE simulations for technology evaluation and design optimization
Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
Nice to have: Experience with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries
Nice to have: Experience with memory products including DRAM, HBM, or SRAM
Nice to have: Knowledge of TSV technologies, Advanced packaging, Reliability modeling and aging simulations, Advanced BEOL technologies, PDK development and validation
Nice to have: Experience leading technology pathfinding and node selection activities
Lead the design, verification, and documentation of high‑performance CMOS analog blocks for custom ASICs, focusing on DDR I/O interfaces and high‑precision analog circuits.
Responsibilities
Architect, design and verify CMOS analog blocks for custom ASICs
Develop and optimize high‑speed DDR I/O interfaces ensuring signal integrity and noise immunity
Liaise between Analog Design Team and Verification/Validation/Test teams
Analyze Si ATE/Bench data and extract actionable information using Excel/MATLAB/scripts
Collaborate with digital design engineers, systems engineers, and other stakeholders
Requirements
Advanced degree in Electronics/Microelectronics Engineering or related discipline
Generate and validate IBIS models for DDRn, LPDDRn, HBM, and UCIe memory interface IP products, ensuring compliance with industry standards; develop timing characterization data and customer-facing timing collateral; extract behavioral models from transistor-level simulations; debug model discrepancies and support signal integrity closure for high-speed memory interfaces.
Compensation
Your recruiter will provide more details about the salary range and benefits during the hiring process.
Responsibilities
Generate and validate IBIS models for DDRn, LPDDRn, HBM, and UCIe memory interface IP products
Develop timing characterization data and customer-facing timing collateral for board-level design and signal integrity analysis
Extract behavioral models from transistor-level simulations and correlate them against silicon characterization results across PVT corners
Work with analog design teams to capture circuit behavior and ensure models reflect real silicon performance
Debug model discrepancies, timing violations, and signal integrity issues reported by customers or internal validation teams
Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field
Senior Signal Integrity Engineer responsible for ensuring performance and reliability of high-speed SerDes IP across silicon, package, and board levels.
Responsibilities
Provide implementation guidelines and feedback to silicon, package, board, and system design teams.
Design and simulate high-speed SerDes signals and perform co-simulation of package and PCB in HFSS.
Conduct feasibility studies, design verification, and sign-off processes, including lab correlation.
Work closely with backend, package, and board design teams for bump-out and ball-out optimization.
Drive chip-package-PCB co-design of SerDes at 112Gbps and beyond, ensuring signal integrity best practices.
Requirements
M.Sc. or Ph.D. in Electrical Engineering, Electromagnetics, Physics, or a relevant related field.
Nice to have: Familiarity with networking technologies and high-speed connectivity solutions
Nice to have: strong analytical and problem-solving skills
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