Develop and execute market access strategies for CST therapies and procedures, evaluate reimbursement dynamics, create value resources, and lead education programs.
Compensation
Salary ranges for U.S (excl. PR) locations (USD):$101,600.00 - $152,400.00
Responsibilities
Develop market access and reimbursement strategies
Assess coding, coverage, and payment dynamics
Create reimbursement, health economics, and procedural value resources
Partner with cross-functional teams
Lead reimbursement and economic education programs
Renesas is looking for an experienced Staff Design Verification Engineer to join our team developing leading-edge memory interface products for data center, AI, and cloud computing applications.
Locations (2)
Orlando, Florida, United States
Duluth, Georgia, United States
Responsibilities
Drive verification activities for complex digital designs at the block and system level.
Develop and execute verification plans based on functional and performance specifications.
Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
Develop verification tests, functional coverage, checkers, and other verification components.
Take ownership of verification environments and verification execution for assigned blocks and features.
Drive verification activities for complex digital designs at the block and system level.
Develop and execute verification plans based on functional and performance specifications.
Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
Develop verification tests, functional coverage, checkers, and other verification components.
Take ownership of verification environments and verification execution for assigned blocks and features.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
Lead verification of advanced memory data buffer products, including DDR6 and future generations, using SystemVerilog and UVM.
Responsibilities
Drive verification activities for complex digital designs at the block and system level.
Develop and execute verification plans based on functional and performance specifications.
Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
Develop verification tests, functional coverage, checkers, and other verification components.
Take ownership of verification environments and verification execution for assigned blocks and features.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
Lead technical verification of advanced semiconductor memory interface products, driving strategy, execution, and mentorship across projects.
Locations (2)
Raleigh, North Carolina, United States
Duluth, Georgia, United States
Responsibilities
Provide technical leadership for verification of complex semiconductor designs at the block and system level.
Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
Drive verification execution, functional coverage, debugging, and coverage closure.
Take ownership of significant verification efforts and make independent technical decisions regarding verification methods, techniques, and priorities.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
Lead technical verification of advanced memory interface products for data center, AI, and cloud computing applications.
Locations (2)
Melbourne, Florida, United States
Duluth, Georgia, United States
Responsibilities
Provide technical leadership for verification of complex semiconductor designs at the block and system level.
Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
Drive verification execution, functional coverage, debugging, and coverage closure.
Take ownership of significant verification efforts and make independent technical decisions regarding verification methods, techniques, and priorities.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Lead technical verification of advanced semiconductor memory interface products for data center, AI, and cloud computing applications.
Responsibilities
Provide technical leadership for verification of complex semiconductor designs at the block and system level.
Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
Drive verification execution, functional coverage, debugging, and coverage closure.
Take ownership of significant verification efforts and make independent technical decisions regarding verification methods, techniques, and priorities.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
Lead verification strategy and execution for complex semiconductor designs, providing technical leadership and mentorship in SystemVerilog/UVM environments.
Locations (2)
Reston, Virginia, United States
Duluth, Georgia, United States
Responsibilities
Lead verification strategy and execution for complex semiconductor designs at the block and system level
Define verification methodologies, test plans, coverage strategies, and verification environments
Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments
Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure
Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field