Referso Jobs

Staff Engineer Verification - Ethernet devices

Infineon · Posted Nov 9, 2026

Open

Dallas, Texas, United States
$99K–$136K per year
1+ years

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Staff Engineer Verification - Ethernet devices

Infineon · Posted Nov 9, 2026

Open

Dallas, Texas, United States
$99K–$136K per year
1+ years

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MTS Silicon Design Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

Boxborough, Massachusetts, United States
3+ years

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Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, focusing on ASIC development and verification.

Responsibilities

Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing
Oversee definition, design, verification, and/or documentation for ASIC development
Determine architecture design, logic design, and/or system simulation
Define module interfaces/formats for simulation
Lead the development of multidimensional designs involving the layout of complex integrated circuits

Requirements

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
Bachelor’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field

Skills

SOC-level ASIC verification Conducting SoC tape‑outs from initial design to the first boot Debugging firmware and RTL code using simulation tools

Senior Digital ASIC Verification Engineer

Ciena · Posted Nov 4, 2026

Open

Ottawa, Ontario, Canada
On-site
Full-time · Senior
CA$112K–CA$179K per year
5+ years

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Senior Digital ASIC Verification Engineer

Compensation

Pay Range: The annual salary range for this position is $111,900 - $178,700 CAD.

Responsibilities

Take ownership of complex top-level and cross-IP verification activities, from verification planning through execution, debug, coverage analysis, and closure.
Develop and maintain SystemVerilog/UVM functional verification environments, testbenches, testcases, checkers, assertions, and supporting verification infrastructure.
Develop cross-IP and system-level test scenarios that exercise interactions, data flows, and dependencies across multiple functional blocks.
Translate architecture, design specifications, and system requirements into comprehensive verification plans and test strategies.
Work closely with designers, architects, and verification engineers to identify verification risks, corner cases, and potential gaps early in the development cycle.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline
Nice to have: formal verification
Nice to have: SVA
Nice to have: large ASICs
Nice to have: SoCs

Skills

SystemVerilog

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