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1–3 jobs· newest first

R&D EngineerNew
Vertiv · United Arab Emirates
Full-time · Mid
Memory PHY - Technical Lead
Advanced Micro Devices, Inc. (AMD) · Markham, Canada+2 more
Mixed Signal & Analog Circuit Engineer
Leadstack Inc

+10K new in the last hour

R&D Engineer

Vertiv · Posted Nov 9, 2026

United Arab Emirates
Full-time · Mid
3–7 years

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Contribute to the innovation and enhancement of the busbar trunking product line, including design, development, and support for new products.

Responsibilities

Define product specifications, features, and functionalities, while ensuring adherence to safety and regulatory standards.
Develop product designs in accordance to Product Standards (for example, IEC61439 & UL857).
3D modelling and 2D drafting of product designs.
Align with the culture of innovation within the product development team.
Work closely with external suppliers and partners to source components and materials.

Requirements

Bachelor’s degree in Electrical engineering
Bachelor’s degree in Mechanical engineering
Bachelor’s degree in design technology
Nice to have: power distribution applications
Nice to have: data center industry

Skills

3D modelling Creo Solidworks 2D drafting GD&T PLM software NPDI NPD DFM DFA DFE PFMEA Control plan PLM PDM/PD Cloud Smartsheet Microsoft Office

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Memory PHY - Technical Lead

Advanced Micro Devices, Inc. (AMD) · Posted Sep 10, 2026

Markham, Ontario, Canada +2 more

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Lead technical integration and support of third‑party Memory/Serdes PHY and mixed‑signal IP across AMD products.

Locations (3)

Markham, Ontario, Canada
Vancouver, British Columbia, Canada
Ottawa, Ontario, Canada

Responsibilities

Serve as AMD technical owner for selected third‑party Memory/Serdes PHY and mixed‑signal IP across multiple product programs.
Provide technical leadership for the IP/PHY throughout the product lifecycle, from architecture to production.
Collaborate directly with third‑party IP vendors to support IP evaluation, design transfer, release collateral, and integration into AMD SoCs.
Partner with SoC integration teams to ensure electrical, logical, and physical quality of IP integration.
Drive system‑level architectural decisions balancing performance, power, area, cost, and implementation constraints.

L

Mixed Signal & Analog Circuit Engineer

Leadstack Inc · Posted Nov 3, 2026

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Architecture and design of high-speed I/O circuit blocks such as TX, PLL, CDR, Analog Front-End (AFE/CTLE), DFE.

Responsibilities

Present architecture and design reviews of key circuits to the rest of the team and counterpart team at headquarters

Requirements

Master in Electrical Engineering or more

Skills

mixed-signal circuit design PLL DLL CDR DFE TX analog front-end (AFE/CTLE)lab measurement serial link characterization

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Requirements

B.S. or M.S. Electrical Engineering

Skills

high‑speed mixed‑signal IP design system‑level architecture integration IP into SOC high‑speed I/O SerDes Memory PHY architectures CTLE FFE DFE VGA CDR PLL/DLL TX driver EMC GPIO HBM LPDDR DDR GDDR PCIe Ethernet USB DisplayPort HDMI MIPI advanced FinFET semiconductor technologies RTL logic design digital circuits Python Perl UNIX environment laboratory equipment (BERT, oscilloscope, logic analyzer)UNIX

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