- Vietnam
- Mid
- 2–3 years
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes.
Responsibilities
- Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN (Power Delivery Network) planning
- Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite
- Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations
- Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus
- Run and debug Design Rule Checking (DRC), Layout Versus Schematic (LVS), Antenna checks, and Electrical Rule Checking (ERC)
Requirements
- Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics
- Nice to have: Cadence Suite