- Cupertino, California, United States
- On-site
- $174K–$225K per year
Collaborating with the logic design team to understand partition architecture and proactively addressing physical design aspects early in the development cycle.
Compensation
The base pay range for this role is between $174,149 - $225,300/yr
Responsibilities
- Managing the complete netlist-to-GDSII implementation process for design partitions
- Ensuring project schedules and design objectives are met
- Performing timing analysis, physical and electrical verification, and driving signoff closure for the partitions
- Working closely with the architecture team to define, analyze, and document the micro-architecture specifications of various hardware design blocks
- Conducting feasibility analyses on proposed architectures and algorithms
Requirements
- Master’s Degree in Electrical and Computer Engineering or related field