- Bangalore, Karnataka, India
- Senior
- 6+ years
Senior modeling engineer focused on memory IP development and optimization for ASIC design flows.
Responsibilities
- Lead memory modeling and compiler development projects
- Write model templates for integration into memory compilers
- Participate in forums for model development and reviews
- Communicate and document project progress
- Improve memory models and generation flows
Requirements
- Bachelor's degree in EE/CS/CE
- Master's degree in EE/CS
- Ph.D. in EE/CS
- Nice to have: 5+ years Verilog modeling experience
- Nice to have: Experience with memory model verification/QC flow