- San Jose, California, United States
- $221K–$221K per year
- 8+ years
1–5 jobs· newest first
$221K–$221K
Senior

$100K–$245K
+10K new in the last hour
Lead validation and characterization of silicon IPs for FPGA products, driving new silicon product bring‑up, debugging, and customer issue resolution.
Base Pay Range 220800
Senior Engineer, Post Silicon Validation
Validate and characterize silicon IPs on FPGA boards, develop test plans, and support product release.
Senior Silicon Design Validation Engineer
Design, integrate, and deliver custom end-to-end RF communications systems built around software defined radios for special operations and intelligence communities.
The referenced pay range is based on JHU APL’s good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. Minimum Rate $100,000 Annually Maximum Rate $245,000 Annually