Architect and drive the AI Software Stack by establishing best practices and optimizing performance from the lowest-level GPU kernels to large-scale distributed systems.
Responsibilities
Architect and drive the AI Software Stack
Optimize performance from lowest-level GPU kernels to large-scale distributed systems
Leverage Large Language Models (LLMs) and agent-based technologies to accelerate the AMD ROCm ecosystem
Accelerate applications such as foundation models and autonomous AI agents
Contribute to the entire co-design lifecycle, influencing future GPU architectures
Senior Silicon Design Engineer to co‑design the hardware‑software interface for AMD Instinct GPUs, modeling performance and power across the AI compute stack.
Locations (2)
San Jose, California, United States
Bellevue, Washington, United States
Responsibilities
Build performance and power models linking architectural decisions to real workload behavior
Evaluate hardware features and software API designs against AI training and inference targets
Write and optimize GPU kernels and compiler passes for microarchitectural characteristics
Work across the stack including Linux kernel DRM/GEM, ROCm runtime, IREE compiler, and AI frameworks like PyTorch and Triton
Leverage performance models to drive software optimization and hardware design feedback
Requirements
Bachelor's in Computer Science
Master's in Computer Science
Nice to have: Experience with AMD Instinct GPU architectures (MI300X, MI350X, MI355X)
Performance & Debug Software Engineer – AI Inference
This engineer will improve end-to-end large language model (LLM) inference performance on Positron's custom AI accelerators, including our FPGA-based Atlas systems and our Titan systems built on the Asimov ASIC.
Compensation
The base salary range for this role is $200,000 – $300,000.
Responsibilities
Profile and optimize latency, throughput, utilization, and efficiency across hardware-accelerated attention, accelerator configuration, the device runtime, host software, and on-device execution.
Use performance counters, hardware and software traces, telemetry, and simulation to isolate regressions and validate fixes.
Develop and optimize distributed inference capabilities, including efficient KV cache management and data movement across heterogeneous hardware.
Build representative benchmarks and workload traces that expose bottlenecks in compute, memory, chip-to-chip interconnect, networking, scheduling, and model loading.
Partner with test engineers embedded in the team to turn performance findings into durable regression tests and release gates.
Implement and extend core driver abstractions and multi-accelerator communication primitives for high-performance systems.
Locations (3)
United States
Canada
Los Altos, California, United States
Compensation
The estimated base salary range for this role to be performed in the US, regardless of the state, is $148,000.00–$270,000.00 USD.
Responsibilities
Implement and extend core driver abstractions — Device, Context, Queue, Memory, Function (kernel representation and launch) — across diverse hardware backends
Contribute to multi-accelerator and multi-node communication and collectives primitives
Improve diagnostics and error reporting across our asynchronous execution stack
Partner with peer teams to build and refine the surfaces they consume in the Mojo standard library and MAX framework
Advanced AI Workloads - Performance and Scalability Engineer
Optimizing and developing deep learning frameworks for AMD GPUs, focusing on GPU kernels, models, and performance across multi-GPU systems.
Responsibilities
Build and optimize end to end distributed inference (e.g, P/D disaggregation and Large-EP) and RL solutions on mainstream frameworks like vLLM and SGlang
Collaborate with GPU Library Teams to analyze and improve training and inference performance on AMD GPUs
Engage with framework maintainers to ensure code changes are aligned with requirements and integrated upstream
Optimize deep learning performance on both scale-up (multi-GPU) and scale-out (multi-node) systems
Utilize cutting-edge compiler technologies to improve deep learning performance
Requirements
Master’s or PhD in Computer Science, Computer Engineering, Electrical Engineering, or related fields
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