- Fort Collins, Colorado, United States
- On-site
- Full-time · Senior
- $110K–$176K per year
- 8–6 years
DFT Engineer for ASIC/Chip level ATPG
Compensation
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
Responsibilities
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns
- Collaborate closely with STA and design integration engineers for timing and design closure
- Generate, verify, and debug test vectors prior to tapeout release
Requirements
- Bachelors in Electrical/Electronic/Computer Engineering
- Masters Degree in Electrical/Electronic/Computer Engineering
- Nice to have: In-Field testing solutions
- Nice to have: ATE silicon bring-up
- Nice to have: high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN)