- Santa Clara, California, United States
- Senior
- $182K–$273K per year
- 13+ years
Lead and architect DFT/Test methodology for complex mixed-signal SOCs across multiple generations, mentoring a team of DFT engineers and driving new methodologies.
Compensation
Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum
Responsibilities
- Architect and lead DFT/Test methodology
- Implement DFT/DFX features
- Validate and debug designs
- Mentor and guide DFT engineers
- Define and enhance DFT methodologies and tools
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields
- Nice to have: Prior experience in ASIC design