In this role, you’ll work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology and developing custom silicon solutions for Google.
Own the planning, creation and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume.
Resolve structural or physical issues related to the integration of complex ASICs and SOCs and collaborate with teams across Google to develop ideas for high impact Silicon and hardware projects.
Manage all cross-functional interactions related to top-level floorplanning of chip projects.
Develop and improve floorplan implementation methodologies.
Support and execute implementation flows using both industry-standard and specialized internal tools.
Requirements
Bachelor's degree in Electrical Engineering
Computer Engineering
Computer Science
a related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science
Lead SRAM design engineer responsible for developing high-performance, low-power embedded memory IP and testchip content across the full memory-development lifecycle.
Compensation
$153,000.00 - $267,000.00 a year
Responsibilities
Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation and waveform/debug reviews.
Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
Requirements
BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field
SoC Silicon Top-Level Floorplan EngineerGoogle · Sunnyvale, US