Implement and optimize low-power design methodologies, perform block- and full-chip-level power analysis, and collaborate with RTL design teams.
New York City Metro Area: $125,700.00 - $203,100.00; Non-Metro New York state & Washington state: $111,700.00 - $180,800.00
- Implement and optimize low-power design methodologies (clock gating, power gating, multi-Vt, dynamic voltage and frequency scaling, and UPF/CPF power intent.
- Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower (PTPX) across various operating modes, PVT corners, and functional activity scenarios (VCD/FSDB/SAIF).
- Collaborate closely with RTL design, architecture teams to identify power bottlenecks and guide RTL/micro-architectural power optimizations.
- Achieve timing closure, signal integrity, and power targets across advanced process nodes (FinFET / GAA).
- Develop and maintain automated design and analysis workflows using Python, TCL, and Perl.
- Bachelors degree + 2 years of relevant experience
- Master’s degree program
- Nice to have: FSDB/VCD/SAIF waveforms
- Nice to have: Synopsys Design Compiler
- Nice to have: Fusion Compiler
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