Talented engineer to join the CPU design team to drive performance verification and correlation between RTL and the performance model for a CPU based on RISC-V ISA.
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Compensation
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets.
Responsibilities
Join a team driving improvements in CPU microarchitecture, verify performance and correlate RTL against the performance model.
Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
Draft performance testplans and develop targeted microbenchmarks to exercise performance features and expose bottlenecks.
Enhance tools and methodologies for performance analysis and correlation to improve development efficiency.
Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.
International Michelin Graduate Program R&D (F/H)
Euromaster France (Michelin Group) · Posted Sep 23, 2025
Identify and formulate open research problems in how AI workloads use and share large-scale compute. Plan and execute original research that advances the state of the art in AI systems and infrastructure.
Locations (2)
Menlo Park, California, United States
New York, New York, United States
Responsibilities
Identify and formulate open research problems in how AI workloads use and share large-scale compute.
Plan and execute original research that advances the state of the art in AI systems and infrastructure, from new abstractions and algorithms to rigorous empirical evaluation.
Collaborate with research scientists and engineers to translate findings into published work and open artifacts.
Communicate results clearly to both specialist and non-specialist audiences.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.
Responsibilities
Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap.
Develop architectural and microarchitectural power/performance models, microarchitecture and evaluate quantitative and qualitative performance and power analysis.
Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software co-design, creating high performance hardware/software interfaces.
Evaluate different silicon solutions for executing Google’s data center Artificial Intelligence (AI) accelerator roadmap, components, vendor co-developments, custom designs and chiplets.
Create high performance hardware/software interfaces.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Nice to have: experience working with software teams optimizing the hardware/software interface
Nice to have: experience in estimating performance by analysis, modeling, and network simulation
Nice to have: experience in programming languages (e.g., C++, Python)
Senior Silicon Design Engineer to co‑design the hardware‑software interface for AMD Instinct GPUs, modeling performance and power across the AI compute stack.
Locations (2)
San Jose, California, United States
Bellevue, Washington, United States
Responsibilities
Build performance and power models linking architectural decisions to real workload behavior
Evaluate hardware features and software API designs against AI training and inference targets
Write and optimize GPU kernels and compiler passes for microarchitectural characteristics
Work across the stack including Linux kernel DRM/GEM, ROCm runtime, IREE compiler, and AI frameworks like PyTorch and Triton
Leverage performance models to drive software optimization and hardware design feedback
Requirements
Bachelor's in Computer Science
Master's in Computer Science
Nice to have: Experience with AMD Instinct GPU architectures (MI300X, MI350X, MI355X)
Lead end-to-end AI workload optimization strategy, driving performance across AMD’s AI software stack.
Responsibilities
Set the technical vision and roadmap for workload optimization across the AI software stack
Lead the profiling, analysis, and tuning of large-scale models to ensure out-of-the-box performance on AMD hardware
Partner with top customers and hyperscalers to understand unique workload requirements and deliver tailored architectural wins and software optimizations
Collaborate across hardware architecture, compiler, and framework teams to influence future silicon features
Drive the development of advanced tools and frameworks for performance estimation, modeling, and automated reporting
Requirements
PhD or Master’s degree in Computer Science, Electrical Engineering, or related field
Nice to have: High-level technical leadership
Nice to have: AI frameworks (PyTorch, JAX, vLLM, SGLang)
Principal of Machine Learning Infrastructure Researcher
Responsibilities
Stay up to date on the latest advancements in Machine Learning research.
Build tools to model the performance of Passage-enabled systems when running both training and inference workloads for the latest AI models.
Collaborate with our product and solutions architecture teams to design compelling reference platforms for our customers, powered by Lightmatter technology.
Function as the Machine Learning expert in the room.
Publish academic papers at top industry conferences and journals. Help support the publication of whitepapers, blog posts, and other marketing collateral.
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