Senior/Lead VLSI Design Engineer responsible for architecting and optimizing global circuit areas including custom clocking, low-power design, and power distribution integrity for SambaNova’s AI accelerators.
Compensation
$210,000—$280,000 USD
Responsibilities
Architect, design, and perform transistor level circuit design and optimization of custom ultra-low-jitter, low-skew chip-level clock distribution networks
Perform comprehensive signal integrity, power integrity, jitter, skew, and EM/IR analyses across all chip-level clock distribution networks
Involved in low-power design methodology and power analysis of key components
Collaborate closely with Physical Design teams on floor-planning, custom routing, shielding strategies, and Clock Tree Synthesis guidelines
Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, primary/secondary ESD clamps, and rail protection structures
Requirements
Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics
Lead the design and development of advanced networking and wireless hardware products across the full hardware lifecycle, from architecture and schematic design through validation, manufacturing, and production release.
Locations (2)
Taipei, Taipei City, Taiwan
Hsinchu, Hsinchu City, Taiwan
Responsibilities
Lead the design and development of advanced networking and wireless hardware products across the full hardware lifecycle, from architecture and schematic design through validation, manufacturing, and production release.
Design complex multilayer and HDI PCBs, define stack-ups, and develop mixed RF/digital layouts.
Perform signal integrity and power integrity analysis using industry-standard simulation tools.
Support EMC/ESD compliance and implement DFM/DFT practices.
Design PoE and DC-DC power systems, including power sequencing.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
T
Network Engineer
Talent Software Services, Inc. · Posted Nov 3, 2026
Hardware architecture design for next generation router and network switch products.
Locations (2)
San Jose, California, United States
California, United States
Responsibilities
Hardware architecture design for next generation router and network switch product development
Actively working in high-speed interface design and analysis, including support 800G line cards and other complex signals
Requirement analysis and selection of key components for major interfaces like Processor SoC, DDR memory, GPU, FPGA, Network switch, PCIe Switch, Clock, Power management devices
Work on electronic products through hardware architecture finalization, high level design, critical components selection, schematics capture and design analysis
Providing PCB stack-up model and extract from tool to meet product PCB thickness, electrical signal speed, power architecture and trace impedance requirements
Skills
Senior Manager of Electrical Engineering, Compute & Sensing
Lead the team responsible for the "nervous system" and "brain" of next-generation humanoid robots, overseeing design of custom high-speed carrier boards and integration of diverse sensor modalities.
Responsibilities
Recruit, hire, and retain top-tier electrical engineers specializing in high-speed digital design, signal integrity, and embedded systems.
Provide deep technical guidance during design reviews, ensuring the team adheres to best practices for PCB layout, thermal management, and EMI/EMC compliance.
Collaborate with Software and Perception leads to define the hardware roadmap for next-generation compute architecture.
Lead the development of custom, ruggedized carrier boards for high-performance SoMs (specifically NVIDIA).
Oversee the implementation and validation of high-speed data protocols.
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Senior/Lead VLS Engineer - Global CircuitsSambaNova Systems · San Jose, US
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