Signal and Power Integrity Engineer
Cisco · Bangalore, India
Signal Integrity Engineer – Memory Interface
Apple · Austin, US+2 more On-site
Signal Integrity Engineer – Memory Interface
Apple · Austin, US+2 more On-site
Signal Integrity Engineer – Memory Interface
Apple · Austin, US+2 more On-site · Full-time · Mid
Signal Integrity Engineer – Memory Interface
Apple · Austin, US+2 more On-site · Full-time · Senior
Signal Integrity Engineer – Memory Interface
Apple · Austin, US+2 more On-site
Signal Integrity Engineer – Memory Interface
Apple · Austin, US+2 more On-site
Signal and Power Integrity Engineer
Cisco · Bangalore, IndiaOn-site · Full-time · Mid
+10K new in the last hour
Cisco · Posted Nov 5, 2026
Responsible for delivering system-level signal and power integrity solutions for high-speed systems, boards and packages, developing SI rules, reviewing design implementation, building test plans, and documenting characterization and measurement reports.
Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports. Improve & optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations for high-speed designs. Design & characterize test structures & channel models to correlate simulations with measurements for Serdes and interconnects. Collaborate with multi-functional teams - HW, PCB Layout, SW, MFG, ASIC. Be responsible for electrical characterization and verification of Transmitter/Receiver SERDES settings to meet industry standards and internal Cisco requirements. Bachelor's or Master’s Degree in Electrical Engineering Apple · Posted Nov 5, 2026
Austin, Texas, United States +2 more On-siteSignal Integrity Engineer – Memory Interface
Austin, Texas, United States San Diego, California, United States Santa Clara, California, United States Work on electrical and physical design of memory systems Work on electrical extraction and validation of package and MLB Work with circuit and controller team to optimize memory system design Work on SI and PI modeling, simulation, and characterization of memory interface Develop and execute test plans to validate signal and power integrity Bachelor's degree Nice to have: MSEE Nice to have: 5+ years of industry experience Apple · Posted Nov 5, 2026
Austin, Texas, United States +2 more On-siteResponsible for memory interface signal integrity for Apple SoCs, covering package to board.
Austin, Texas, United States San Diego, California, United States Santa Clara, California, United States Work on electrical and physical design of memory systems Work on electrical extraction and validation of package and MLB Work with circuit and controller team to optimize memory system design Work on SI and PI modeling, simulation, and characterization of memory interface Develop and execute test plans to validate signal and power integrity Bachelor's degree Nice to have: MSEE Apple · Posted Nov 5, 2026
Austin, Texas, United States +2 more On-site Full-time · Mid 5+ yearsSignal Integrity Engineer focused on memory interface signal integrity for Apple SoCs in mobile devices, covering the span from package to board.
Austin, Texas, United States San Diego, California, United States Santa Clara, California, United States You will work on electrical and physical design of memory systems Work on electrical extraction and validation of package and MLB Work with circuit and controller team to optimize memory system design Work on SI and PI modeling, simulation, and characterization memory interface Develop and execute test plans to validate signal and power integrity Apple · Posted Nov 5, 2026
Austin, Texas, United States +2 more On-site Full-time · Senior 10+ yearsResponsible for memory interface signal integrity for Apple SoCs, covering the span from package to board, including electrical and physical design of memory systems.
Austin, Texas, United States San Diego, California, United States Santa Clara, California, United States Work on electrical and physical design of memory systems. Work on electrical extraction and validation of package and MLB. Work with circuit and controller team to optimize memory system design. Work on SI and PI modeling, simulation, and characterization memory interface. Develop and execute test plans to validate signal and power integrity. Apple · Posted Nov 5, 2026
Austin, Texas, United States +2 more On-site 10+ yearsAustin, Texas, United States San Diego, California, United States Santa Clara, California, United States Work on electrical and physical design of memory systems Work on electrical extraction and validation of package and MLB Work with circuit and controller team to optimize memory system design Work on SI and PI modeling, simulation, and characterization of memory interface Develop and execute test plans to validate signal and power integrity Bachelor's degree Master's degree PhD Nice to have: MSEE Nice to have: PhD Apple · Posted Nov 5, 2026
Austin, Texas, United States +2 more On-site 10+ yearsResponsible for memory interface signal integrity for Apple SoCs, covering package to board.
Austin, Texas, United States San Diego, California, United States Santa Clara, California, United States Work on electrical and physical design of memory systems Work on electrical extraction and validation of package and MLB Work with circuit and controller team to optimize memory system design Work on SI and PI modeling, simulation, and characterization memory interface Develop and execute test plans to validate signal and power integrity Cisco · Posted Nov 5, 2026
Bangalore, Karnataka, India On-site Full-time · Mid 4–7 yearsDelivering system-level signal and power integrity solutions for large sophisticated high-speed systems, boards & packages.
Deliver system-level signal and power integrity solutions for large sophisticated high-speed systems, boards & packages. Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports. Improve & optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations for high-speed designs. Design & characterize test structures & channel models to correlate simulations with measurements for Serdes and interconnects. Collaborate with multi-functional teams - HW, PCB Layout, SW, MFG, ASIC. Bachelor's Degree in Electrical Engineering Master’s Degree in Electrical Engineering Nice to have: 56G PAM4 Nice to have: 25G NRZ Serdes Nice to have: 10G NRZ Serdes
Nice to have: Ph.D.
Nice to have: 5+ years industry experience
Nice to have: Ph.D.
bachelors degree
MSEE
Ph.D.
Nice to have: VNA
Nice to have: TDR
BS
MSEE
Ph.D.
Nice to have: Product package/board design and analysis
Nice to have: PI/SI methodology development
Nice to have: MSEE
Nice to have: Ph.D.