Referso Jobs

ASIC DFT Engineer

Broadcom · Posted Nov 11, 2026

Open

Fort Collins, Colorado, United States
On-site
Full-time · Senior
$129K–$207K per year
12–10 years

ASIC DFT Engineer

Broadcom · Posted Nov 11, 2026

Open

Fort Collins, Colorado, United States
On-site
Full-time · Senior
$129K–$207K per year
12–10 years

ASIC DFT Engineer

Broadcom · Posted Nov 11, 2026

Open

Fort Collins, Colorado, United States
On-site
Full-time · Senior
$129K–$207K per year
12–10 years

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DFT Engineer for ASIC/Chip level ATPG

Compensation

The annual base salary range for this position is USD 129,400.00 To USD 207,000.00

Responsibilities

Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC
Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns
Collaborate closely with STA and design integration engineers for timing and design closure
Generate, verify, and debug test vectors prior to tapeout release

Requirements

Bachelors in Electrical/Electronic/Computer Engineering
Masters Degree in Electrical/Electronic/Computer Engineering
Nice to have: In-Field testing solutions
Nice to have: ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN)

Skills

DFT architecture and implementation (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)EDA tools (DFT Compiler, TestKompress, TetraMax, FastScan)

ASIC DFT Engineer

Broadcom · Posted Nov 11, 2026

Open

Fort Collins, Colorado, United States
On-site
Full-time · Senior
$110K–$176K per year
8–6 years

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DFT Engineer for ASIC/Chip level ATPG

Compensation

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

Responsibilities

Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC
Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns
Collaborate closely with STA and design integration engineers for timing and design closure
Generate, verify, and debug test vectors prior to tapeout release

Requirements

Bachelors in Electrical/Electronic/Computer Engineering
Masters Degree in Electrical/Electronic/Computer Engineering
Nice to have: In-Field testing solutions
Nice to have: ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN)

Skills

DFT architecture and implementation (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)Proficiency with EDA tools (DFT Compiler, TestKompress, TetraMax, FastScan)

ASIC DFT Engineer

Broadcom · Posted Nov 11, 2026

Open

Fort Collins, Colorado, United States
On-site
Full-time · Senior
$110K–$176K per year
8–6 years

Apply with RefersoAI Apply on careers page

DFT Engineer for ASIC/Chip level ATPG

Compensation

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

Responsibilities

Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC
Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns
Collaborate closely with STA and design integration engineers for timing and design closure
Generate, verify, and debug test vectors prior to tapeout release

Requirements

Bachelors in Electrical/Electronic/Computer Engineering
Masters Degree in Electrical/Electronic/Computer Engineering
Nice to have: In-Field testing solutions
Nice to have: ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN)

Skills

DFT architecture and implementation (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)Proficiency with EDA tools (DFT Compiler, TestKompress, TetraMax, FastScan)

ASIC DFT Engineer

ASIC DFT Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

ASIC DFT Engineer

Compensation

Responsibilities

Requirements

Skills

ASIC DFT Engineer

Compensation

Responsibilities

Requirements

Skills

ASIC DFT Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

Benefits

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