Verification Infrastructure jobs

Sr Design Verification Eng

Lattice Semiconductor · Posted Sep 4, 2026

Open

Pune, Maharashtra, India
Senior
6+ years

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Sr Design Verification Eng

Lattice Semiconductor · Posted Sep 4, 2026

Open

Pune, Maharashtra, India
Senior
6+ years

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NOC Design Verification Sr Engineer

Qualcomm · Posted Nov 3, 2026

Open

Noida, Uttar Pradesh, India
Full-time · Senior
4+ years

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Lead design verification for ASIC and embedded IPs, creating UVM-based test benches and verification methodologies.

Responsibilities

Create state‑of‑the‑art UVM test benches and methodologies
Define test plans, tests and verification infrastructure for modules, IPs and sub‑systems
Build efficient and reusable bus functional models, monitors, checkers and scoreboards
Implement functional coverage and own verification closure
Work with architects and design teams to ensure verification completeness

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
Nice to have: Power Aware Verification

Skills

Design Verification UVM Test Bench Development Test Plan Definition Verification Infrastructure

Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive · Posted Jul 3, 2026

Open

Boston, Massachusetts, United States
Senior
8+ years

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Lead verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs.

Compensation

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.

Responsibilities

Own verification planning and execution for a scalable cache-coherent interconnect subsystem
Define verification strategy, test plans, environments, and closure criteria
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models
Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths
Create high-value directed and constrained-random scenarios

Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Nice to have: formal verification
Nice to have: performance-oriented verification
Nice to have: emulation / FPGA-assisted debug
Nice to have: technical leadership

Skills

SystemVerilog verification infrastructure cache-coherent systems

lead Design Engineer

Cadence Design Systems · Posted Nov 3, 2026

Open

Bangalore, Karnataka, India
On-site
Lead
5+ years

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Lead Design Engineer – UCIe Controller Verification focused on verification of complex UCIe Controller IP, working on next-generation chiplet and die-to-die interconnect solutions.

Responsibilities

Contribute to the verification of complex UCIe Controller IP
Work closely with design, architecture, validation, and other cross-functional teams
Develop scalable verification environments
Validate complex protocol scenarios
Drive coverage closure

Requirements

BE
BTech
ME
MTech
MS

Skills

SystemVerilog UVM Verification architecture coverage-driven verification protocol verification debug Constrained-random verification Functional coverage

Verification Infrastructure jobs

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