- Pune, Maharashtra, India
- Full-time · Lead
- 12–15 years
Guide engineering team and drive physical implementation for Cisco's next-generation silicon photonics driver and receiver ICs, powering 100G, 200G, and 400G-per-lambda Co-Packaged Optics (CPO) and optical engine solutions.
Responsibilities
- Lead, mentor, and technically steer a team of physical design engineers
- Own full-chip and hierarchical block-level RTL-to-GDSII implementation and sign-off on advanced nodes
- Establish advanced physical design methodologies
- Drive floor-planning, place & route, low-skew clock and power distribution, multi-corner timing closure (STA), EM/IR integrity, and DRC/LVS physical verification sign-off
- Partner closely with Architecture, Analog Front-End, Layout, and Photonic packaging teams
Requirements
- Bachelor’s degree or equivalent experience in electrical engineering, Electronics & Communication or related field
- Master's degree (M.S. / M.Tech) in Electrical Engineering, VLSI Design, or Microelectronics
- Nice to have: VLSI Design
- Nice to have: Mixed-Signal & High-Speed IP Integration
- Nice to have: Logic synthesis (Cadence Genus / Synopsys Design Compiler)