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ASIC Development Technical Leader

Cisco · Posted Nov 9, 2026

Vancouver, British Columbia, Canada
Full-time · Lead
$147K–$198K per year
3+ years

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Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.

Compensation

The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Responsibilities

Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks

Requirements

Bachelor’s Degree in Electrical Engineering
Master’s Degree in Electrical Engineering
PhD in Electrical Engineering
Nice to have: Fullchip activities
Nice to have: floor-planning

Skills

Physical Design RTL2GDSII flow

Physical Design Technical Leader | ASIC/SoC physical design

Physical Design Technical Leader | ASIC/SoC physical design

Responsibilities

Requirements

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ASIC Development Technical Leader

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