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Skill:bus functional models (BFMs)

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1–2 jobs· newest first

Design Verification Engineer
Apple · Cupertino, US
$174K–$225KOn-site
NOC Design Verification Sr Engineer
Qualcomm · Noida, India
Full-time · Senior

+10K new in the last hour

Design Verification Engineer

Apple · Posted Nov 5, 2026

Cupertino, California, United States
On-site
$174K–$225K per year

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AI

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Design Verification Engineer

Compensation

base pay range for this role is between $174,149 - $225,300/yr

Responsibilities

Work closely with architecture and RTL designers verifying the functionality correctness of the design
Develop and lead test plans and test environments
Develop complex tests in assembly, C, or vectors according to test plans
Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
Develop checkers or C-based transactor to verify the design

Requirements

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or related field

Skills

CPU architecture system-level behavior root-cause failure analysis waveform and log debugging RTL or testbench fixes transactors bus functional models (BFMs)protocol agents architectural and micro-architectural checkers coverage-driven verification (CDV)functional, assertion, and cross-coverage analysis formal property verification hardware emulation FPGA/SoC bring-up flows security vulnerabilities like Spectre or Meltdown assembly C vectors C++System Verilog Python Verdi

Benefits

Comprehensive medical and dental coverage
retirement benefits
discounted products and free services
reimbursement for certain educational expenses
discretionary restricted stock unit awards

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NOC Design Verification Sr Engineer

Qualcomm · Posted Nov 3, 2026

Noida, Uttar Pradesh, India
Full-time · Senior
4+ years

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Lead design verification for ASIC and embedded IPs, creating UVM-based test benches and verification methodologies.

Responsibilities

Create state‑of‑the‑art UVM test benches and methodologies
Define test plans, tests and verification infrastructure for modules, IPs and sub‑systems
Build efficient and reusable bus functional models, monitors, checkers and scoreboards
Implement functional coverage and own verification closure
Work with architects and design teams to ensure verification completeness

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
Nice to have: Power Aware Verification

Skills

Design Verification UVM Test Bench Development Test Plan Definition Verification Infrastructure

Bus Functional Models

Functional Coverage

Verification Closure

Architectural Collaboration

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