Coverage-driven verification (CDV) jobs

Design Verification Engineer

Apple · Posted Nov 5, 2026

Open

Cupertino, California, United States
On-site
$174K–$225K per year

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Design Verification Engineer

Apple · Posted Nov 5, 2026

Open

Cupertino, California, United States
On-site
$174K–$225K per year

Apply with Referso

AI Accelerator Design Verification Engineer - Intern

RosaicLabs · Posted Oct 5, 2026

Open

Santa Clara, California, United States
On-site
Internship · Intern

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The intern will verify the accelerator with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Responsibilities

Work with your mentor to develop verification plans for the accelerator
Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
Build tests, scoreboards, and reference models, and close functional and code coverage
Triage and root-cause failures with RTL designers, with mentorship from senior engineers
Participate in design and verification reviews and document your verification environment and results

Requirements

BS/MS in Electrical Engineering
Computer Engineering
Computer Science
Nice to have: parallel datapaths
Nice to have: SIMD / SIMT / vector processing

Skills

Digital design Verification computer microarchitecture digital logic and RTL design constrained-random verification

Functional Verification Engineer

Accenture Infrastructure and Capital Projects, LLC · Posted Nov 4, 2026

Open

Bengaluru, Karnataka, India
3+ years

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Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level.

Responsibilities

Develop comprehensive test environments to validate digital hardware components
Collaborate with design and architecture teams to identify edge cases and ensure verification coverage
Create constrained-random, directed, and coverage-driven tests using SystemVerilog and UVM
Analyze simulation results to confirm design integrity
Document verification plans, test cases, and results

Requirements

15 years full time education

Skills

SoC Verification SystemVerilog Universal Verification Methodology constrained-random verification coverage-driven verification directed tests digital design concepts

Functional Verification Engineer

Accenture Infrastructure and Capital Projects, LLC · Posted Nov 4, 2026

Open

Bengaluru, Karnataka, India
3+ years

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Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level.

Responsibilities

Develop and maintain verification environments to support design validation efforts
Analyze verification results and debug issues to improve test coverage and quality
Support junior team members by sharing knowledge and assisting in their development

Requirements

15 years full time education

Skills

SoC Verification SystemVerilog Universal Verification Methodology digital design principles hardware description languages coverage-driven verification debugging simulation results UVM

Functional Verification Engineer

Accenture Infrastructure and Capital Projects, LLC · Posted Nov 4, 2026

Open

Bengaluru, Karnataka, India
On-site
Full-time · Senior
5+ years

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Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM.

Responsibilities

Expected to be an SME, collaborate and manage the team to perform.
Responsible for team decisions.
Engage with multiple teams and contribute on key decisions.
Provide solutions to problems for their immediate team and across multiple teams.
Lead efforts to improve verification methodologies and processes to enhance efficiency and coverage.

Requirements

15 years full time education
Nice to have: PCIe Subsystem/SoC DV
Nice to have: Ethernet/Networking SoC DV
Nice to have: Embedded C
Nice to have: Firmware validation

Skills

SoC Verification SystemVerilog UVM constrained-random testing coverage-driven verification Xcelium

Digital Verification Engineer (all genders)

IMS Nanofabrication GmbH · Posted Nov 3, 2026

Open

Wien, Wien, Austria
Hybrid
Full-time · Senior
€70K per year
5+ years

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In this position you will own the verification strategy, testbench development, and sign-off readiness for assigned IPs, subsystems, or distributed systems.

Compensation

attractive annual gross salary from 70.000 € (plus bonus, KV Metallgewerbe)

Responsibilities

Own the verification planning process for assigned IPs and subsystems, including definition of verification scope, strategy, coverage goals, and resource requirements
Develop and maintain reusable verification environments, testbenches, verification components, and infrastructure using industry-standard methodologies and languages
Ensure complete verification of functional requirements through directed, constrained-random, assertion-based, and coverage-driven verification
Execute verification closure activities by tracking functional, code, assertion, and other relevant coverage metrics against defined project targets
Identify, analyze, and drive resolution of design defects through systematic debug and root-cause analysis in collaboration with design engineering teams

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline

Skills

SystemVerilog

Design Verification Engineer

Design Verification Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

AI Accelerator Design Verification Engineer - Intern

Responsibilities

Requirements

Skills

Functional Verification Engineer

Responsibilities

Requirements

Skills

Functional Verification Engineer

Responsibilities

Requirements

Skills

Functional Verification Engineer

Responsibilities

Requirements

Skills

Digital Verification Engineer (all genders)

Compensation

Responsibilities

Requirements

Skills

Benefits