Gate-level simulation (GLS) jobs

Implement scan, compression, OCC, wrappers and MBIST on assigned blocks/partitions.
Run ATPG, analyze coverage, and drive coverage improvement (test points, fault exclusions).
Run DFT DRC, gate-level (zero-delay and SDF) simulations, and debug failures.
Support DFT timing constraints and closure with PD/STA teams.
Generate patterns and support silicon bring-up and ATE pattern debug.

Requirements

BS/MS in EE/CE

Skills

scan ATPG MBIST JTAG Synopsys Siemens Verilog SystemVerilog

Senior Engineer I - Verification

Microchip · Posted Nov 4, 2026

Open

Chennai, Tamil Nadu, India
On-site
Full-time · Senior
5–10 years

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The WIPD Group role is responsible for the design and pre-silicon verification of wireless devices, focusing on IP and WSS-level verification.

Responsibilities

Perform IP and WSS-level verification of wireless protocols.
Develop IP verification environments and test cases in accordance with WSG-adopted methodologies.
Create verification plans based on IP and product specification documents.
Develop test environments using SystemVerilog and UVM verification methodologies.
Generate code and functional coverage, analyze coverage results, and correlate findings with the verification plan.

Requirements

Bachelor’s or Master’s degree in Electronics Engineering or a related field
Nice to have: AI tools
Nice to have: Machine learning tools

Skills

SystemVerilog UVM IP verification subsystem verification SoC verification C programming

Lead DFT Engineer (Scan Insertion | ATPG | MBIST | JTAG)

Advanced Micro Devices, Inc · Posted Nov 4, 2026

Open

Bangalore, Karnataka, India
Full-time · Lead
12+ years

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As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

Responsibilities

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Nice to have: Design for Test methodologies
Nice to have: DFT verification experience
Nice to have: IEEE1500
Nice to have: JTAG 1149.x

Skills

DFT architecture Scan insertion ATPG pattern generation gate-level simulation Mentor testkompress Synopsys Tetramax

Principal DFT Engineer

Principal DFT Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

Staff Engineer- DFT

Compensation

Responsibilities

Requirements

Skills

Senior Engineer I - Verification

Responsibilities

Requirements

Skills

Lead DFT Engineer (Scan Insertion | ATPG | MBIST | JTAG)

Responsibilities

Requirements

Skills

Benefits

Benefits