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1–2 jobs· newest first

ASIC Design Technical Lead (CPU subsystems)New
Cisco · San Jose, US+5 more
$187K–$268K
ASIC Design Technical Lead (CPU subsystems)New
Cisco · San Jose, US
$187K–$268K

+10K new in the last hour

ASIC Design Technical Lead (CPU subsystems)

Cisco · Posted Nov 9, 2026

San Jose, California, United States +5 more
$187K–$268K per year
3+ years

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AI

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Locations (6)

San Jose, California, United States
New York City, New York, United States
New York, United States
Washington, United States
Illinois, United States
Canada

Compensation

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Responsibilities

Lead the architecture and design of complex CPU subsystems for next‑generation high‑performance networking switch ASICs
Use expertise in all stages of ASIC development from specification and RTL design through post‑silicon bring‑up
Collaborate closely with SDK, board‑support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms

Requirements

Bachelor's degree
Master's degree
PhD
Nice to have: Leading CPU/SoC subsystem architecture
Nice to have: Boot security

Skills

RISC‑V microarchitecture ARM microarchitecture ARC microarchitecture AXI interconnect CHI interconnect NoC interconnect PCIe ASIC/SoC design flow RTL development using SystemVerilog pre‑silicon verification lint CDC/RDC synthesis timing constraints implementation handoff

Benefits

medical insurance
dental insurance
vision insurance
401(k) plan with matching
paid parental leave

See full job description

ASIC Design Technical Lead (CPU subsystems)

Cisco · Posted Nov 9, 2026

San Jose, California, United States
$187K–$268K per year
3+ years

Apply with RefersoAI Apply on careers page

Lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.

Compensation

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Responsibilities

Lead architecture and design of CPU subsystems
Use expertise in all stages of ASIC development from specification and RTL design through post-silicon bring-up
Collaborate closely with SDK, board-support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms

Requirements

Bachelor’s + 8 years of related experience
Master’s + 6 years of related experience
PhD + 3 years of related experience
Nice to have: CPU/SoC subsystem architecture
Nice to have: high-performance networking or data-center SoCs

Skills

RISC-V ARM ARC AXI

post‑silicon bring‑up

pre‑silicon verification tools

synthesis tools

implementation tools

RTL development

pre-silicon verification

implementation handoff

post-silicon bring-up

Benefits

medical
dental
vision
401(k)
paid parental leave

See full job description