- Sunnyvale, California, United States
- On-site
- 8+ years
Responsibilities
- Own power architecture and modeling for ML accelerator IP, from early concept through tape-out and post-silicon correlation
- Build workload-driven power models (energy per op and per byte moved) to evaluate dataflow, memory hierarchy, precision, and sparsity trade-offs before RTL
- Deliver cost/benefit analyses that guide architecture decisions
- Define power management strategy (clock and power gating, DVFS, retention, power states) and set IP-level power budgets aligned with system battery and thermal targets
- Drive hardware-software co-design with ML algorithm, compiler, and firmware teams to optimize power across real use cases
Requirements
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Master's or Ph.D. in EE, CE, CS, or a related field