Protocol compliance testing jobs

Silicon Design Validation, Senior Manager

Lattice Semiconductor · Posted Aug 31, 2026

Open

Pune, Maharashtra, India
Manager
15+ years

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Silicon Design Validation, Senior Manager

Lattice Semiconductor · Posted Aug 31, 2026

Open

Pune, Maharashtra, India
Manager
15+ years

Apply with Referso

Staff Engineer - Post Siiicon Validation

Lattice Semiconductor · Posted Sep 4, 2026

Open

Pune, Maharashtra, India
Full-time · Staff
8+ years

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The ideal candidate is highly motivated in deoping a career in Silicon Design Validation engineering. The role involves validating and characterizing IPs from silicon arrival to production, and driving new silicon product bring-up.

Responsibilities

Validate and characterize various IPs from silicon arrival to release to production
Develop validation and characterization plans for certain IP, bench hardware and software
Develop test logic RTL to achieve intended validation/characterization test
Drive new silicon product bring-up, validation, debug to assess IP functionality/performance
Characterizing data sheet parameters

Requirements

Electrical Engineering degree
Nice to have: FPGA (emulation/prototyping)

Skills

Silicon Design Validation High Speed Serdes Interface characterization protocol compliance testing PCIe/Ethernet/SDI/CoaXpress/JESD204 MIPI D-PHY MIPI CSI/DSI-2

Senior Manager, Post-Silicon Validation Engineering

Lattice Semiconductor · Posted Sep 4, 2026

Open

Pune, Maharashtra, India
Manager
15+ years

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Lead a team focused on ensuring the quality and performance of advanced semiconductor products across the post‑silicon lifecycle.

Responsibilities

Lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products
Provide strategic oversight and technical direction across the full post‑silicon lifecycle
Foster a learning environment for engineers working with FPGA architectures and foundational IP blocks
Oversee validation and characterization of analog, digital, and mixed‑signal IPs
Guide development of validation plans and ensure necessary tools and infrastructure

Requirements

Master or Bachelor’s degree in Electrical Engineering

Skills

high‑speed SerDes interface characterization protocol compliance testing high‑speed board design signal integrity evaluation debug Verilog