Senior Test & Evaluation Engineer responsible for flight and ground testing of B-52 Stratofortress programs, including test planning, execution, data analysis, and customer interaction.
Compensation
Summary Pay Range: $135,150 - $182,850
Responsibilities
Develops and documents standardized test methods and processes to ensure repeatability and productivity
Leads the development of test procedures
Applies lessons learned to the improvement of test procedures
Designs calibration system/test fixtures, develops data processing tools and algorithms
Generates calibration procedures and software
Requirements
Bachelor's Degree in Engineering, Engineering Technology, Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications
This position supports developmental ground and flight testing of the B-52 Stratofortress programs, focusing on test planning, test execution, problem identification and resolution, data collection and analysis, and customer interaction.
Compensation
Summary Pay Range: $135,150 - $182,850
Responsibilities
Develops and documents standardized test methods and processes to ensure repeatability and productivity
Leads the development of test procedures
Applies lessons learned to the improvement of test procedures
Lead and grow infrastructure and validation engineering teams supporting NVIDIA’s Local AI and PC gaming R&D.
Responsibilities
Lead and grow infrastructure and validation engineering teams responsible for CI/CD, test development and automation, regression analysis, failure triage and debugging support, and lab operations, including hardware health, maintenance, and recovery.
Define and drive the team’s technical roadmap, priorities, and delivery commitments across Local AI and PC gaming, balancing long-term infrastructure improvements with day-to-day engineering needs.
Drive the development and deployment of tests and benchmarks that reflect real-world usage, supported by automation for environment setup, test execution, log collection, and results analysis.
Build tools that help reproduce failures and analyze logs and system metrics.
Partner with engineering teams to identify root causes and resolve functional issues and performance bottlenecks across the hardware and software stack.
Requirements
Bachelor's or master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical field
Architect and drive complex pre-silicon verification, including SoC security verification, for Microsoft’s AI accelerators from block to chip and system level through post-silicon validation.
Locations (3)
Redmond, Washington, United States
San Francisco, California, United States
New York City, New York, United States
Compensation
Silicon Engineering IC6 - The typical base pay range for this role across the U.S. is USD $165,600 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.
Responsibilities
Create complex verification environments and tests, driving pre-silicon functional verification at the block, chip, and system level, reference modeling, and post-silicon validation.
Interact with architects and design engineers to create verification plans covering strategy, test environments and tests, and verification requirements for IP, subsystem, and SoC level verification, then create and drive test plans and test development to provide complete feature coverage.
Responsible for all Production Test related collaboration between the Customer's Manufacturing Test Engineering team, R&D team in product development programs and CM, integrating Test HW and SW releases into NPI builds and mass production at the CM site.
Responsibilities
Collaborate with Customer's Manufacturing Test Engineer team to integrate required Test HW and SW releases into NPI builds and mass production at the CM site
Utilize and maintain calibration and preventative maintenance routines
Use data and analysis to show tests are accurate and effective
Monitor daily test yield and failure mechanisms, driving root cause analysis with process teams
Ensure high test coverage to guarantee zero quality escapes to customers
Defining SoC security architecture and threat models, including secure boot, root of trust, identity, isolation, privilege, debug, lifecycle, and recovery.
Develop verification components such as scoreboards, sequences, constraints, assertions, and functional coverage, along with Makefiles and scripts for scalable and efficient verification.
Develop and implement technical solutions to complex quality and design challenges, and triage and debug testbench, simulation, and emulation failures.
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: CPU, graphics, or NPU security architecture
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