Referso Jobs

DFT Senior Engineer

Broadcom · Posted Nov 2, 2026

Open

Bangalore, India
Senior
5+ years

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DFT Senior Engineer

Broadcom · Posted Nov 2, 2026

Open

Bangalore, India
Senior
5+ years

Apply with Referso

DFT Senior Engineer

Broadcom · Posted Nov 2, 2026

Open

Bangalore, India
Senior
5+ years

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Senior Engineer responsible for SoC DFT activities including architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug and yield improvement.

Responsibilities

Work on various phases of SoC DFT related activities for Broadcom APD designs
Collaborate with Physical Design & STA team for DFT mode timing closure
Interact with external customers
Handle work independently across multiple geographies

Requirements

Bachelor's degree with 5+ years of relevant experience
Master's degree with 3+ years of relevant experience

Skills

DFT concepts ATPG MBIST IJTAG DFT insertion verification pattern generation coverage improvement vector simulation

DFT Staff Engineer

Broadcom · Posted Nov 2, 2026

Open

Pune, Maharashtra, India
6+ years

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Lead DFT design, verification, and post-silicon debug for Broadcom ASIC products.

Responsibilities

Design and verify DFT architecture for SoC ASICs
Insert and verify DFT elements such as ATPG, MBIST, IJTAG
Generate test patterns and improve coverage
Perform vector simulation and post-silicon debug
Collaborate with Physical Design & STA teams for timing closure

Requirements

Bachelor's degree in Electrical Engineering or related field
Master's degree in Electrical Engineering or related field

Skills

DFT concepts ATPG MBIST IJTAG pattern generation coverage improvement vector simulation post-silicon debug scripting languages perl shell

DFT Senior Engineer

Broadcom · Posted Nov 2, 2026

Open

Pune, Maharashtra, India
Senior
5+ years

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Lead DFT engineering activities for Broadcom APD ASIC designs, including architecture, test insertion, verification, pattern generation, coverage improvement, and post-silicon debug.

Responsibilities

Design and implement DFT architecture for ASIC products
Insert and verify DFT elements such as ATPG, MBIST, and IJTAG
Generate test patterns and improve coverage
Simulate vectors and debug post-silicon issues
Collaborate with Physical Design & STA teams for timing closure

Requirements

Bachelor's degree
Master's degree

Skills

DFT concepts ATPG MBIST IJTAG DFT insertion DFT verification pattern generation coverage improvement vector simulation

R&D Engineer IC Design

Broadcom · Posted Nov 2, 2026

Open

Bangalore, India
6+ years

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Responsible for SoC DFT activities including architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement.

Responsibilities

Work on DFT architecture, test insertion and verification
Generate patterns and improve coverage
Perform vector simulation and post-silicon debug
Collaborate with Physical Design & STA team for timing closure
Interact with external customers

Requirements

Bachelor’s degree
Master’s degree

Skills

DFT concepts ATPG MBIST JTAG pattern generation coverage improvement vector simulation post-silicon debug perl

R&D Engineer IC Design

Broadcom · Posted Nov 2, 2026

Open

Bangalore, Karnataka, India
6+ years

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Responsibilities

Work on various phases of SoC DFT related activities for Broadcom APD designs
Perform DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement
Collaborate with Physical Design & STA team for DFT mode timing closure
Interact with external customers as needed
Supervise work of other team members when required

Requirements

Bachelor’s degree with 8+ years of relevant experience
Master’s degree with 6+ years of relevant experience
Nice to have: Perl
Nice to have: Shell

Skills

DFT concepts ATPG MBIST JTAG DFT insertion & verification Pattern generation Coverage improvement Vector simulation

STAFF DFT Engineer

Broadcom · Posted Nov 2, 2026

Open

Bangalore, India
Staff
6+ years

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Lead DFT design, verification, and post‑silicon debug for Broadcom ASIC products.

Responsibilities

Design and verify DFT architecture for SoC ASICs
Insert and verify DFT modes including ATPG, MBIST, IJTAG
Generate test patterns and improve coverage
Simulate vectors and debug post‑silicon issues
Collaborate with Physical Design & STA teams for timing closure

Requirements

Bachelor's degree
Master's degree

Skills

DFT concepts ATPG MBIST IJTAG pattern generation coverage improvement vector simulation post‑silicon debug scripting languages

STAFF DFT Engineer

Broadcom · Posted Nov 2, 2026

Open

Bangalore, India
Staff
6+ years

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Design and verification of DFT (Design for Test) for SoC ASICs at Broadcom.

Responsibilities

Design DFT architecture and test insertion
Verify DFT insertion and pattern generation
Improve coverage and debug post-silicon issues
Collaborate with Physical Design & STA team for timing closure
Interact with external customers

Requirements

Bachelor's degree
Master's degree

Skills

DFT concepts ATPG MBIST IJTAG pattern generation coverage improvement vector simulation post-silicon debug scripting languages perl shell

R&D Engineer IC Design

Broadcom · Posted Nov 2, 2026

Open

Bangalore, Karnataka, India
On-site
Full-time · Senior
6–8 years

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The role involves working on various phases of SoC DFT related activities including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post silicon debug, and yield improvement.

Responsibilities

Work on SoC DFT architecture
Test insertion and verification
Pattern generation
Coverage improvement
Post silicon debug and yield improvement

Requirements

Bachelor’s degree
Master’s degree
Nice to have: perl
Nice to have: shell
Nice to have: Seimens-Mentor Graphics DFT tools

Skills

DFT concepts ATPG MBIST JTAG DFT insertion & verification pattern generation coverage improvement vector simulation post-silicon debug

Vector simulation jobs

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