Lead UI modernization and architecture for Lattice EDA tools, driving migration of legacy UI codebases to modern platforms such as QT, while ensuring high performance, accessibility, and user experience excellence.
Responsibilities
Lead UI modernization initiatives
Drive migration of legacy UI codebases into newer, scalable platforms
Define future‑facing user experiences across platforms
Translate marketing requirements into UI architecture and UX flows
Own design intent throughout implementation
Requirements
BS/MS/PhD in Computer Science, Electrical Engineering, HCI, or related field
Senior Design Engineer – Modeling position develops, validates, and delivers IP behavioral models and related hardware collateral used by internal engineering teams and software-facing customers.
Responsibilities
Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
Translate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.
Perform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.
Lead or support the generation, audit, validation, and release of timing, power, signal-integrity, configuration, and metadata deliverables used for hardware and software integration.
Investigate and resolve model behavior, hardware-to-software integration, and customer-facing issues across the IP development lifecycle.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field
Lead the strategy, architecture, development, and operational excellence of CAD and EDA Infrastructure, enabling world-class semiconductor and hardware design teams through scalable design environments, automation, tool optimization, and engineering productivity.
Compensation
Base Pay Range 250,000.00
Responsibilities
Define and execute the vision, roadmap, and strategy for CAD and EDA infrastructure supporting ASIC, SoC, IP, and verification teams.
Lead the design, deployment, and maintenance of highly scalable and secure engineering environments.
Drive infrastructure modernization initiatives including cloud-enabled design workflows, hybrid compute environments, and next-generation engineering platforms.
Partner with design, verification, implementation, and architecture teams to understand evolving tool and infrastructure requirements.
Optimize RTL-to-GDSII design flows across synthesis, place-and-route, STA, DFT, verification, emulation, and signoff.
An integration design engineering role focused on Custom and Digital Design Implementation, specifically using Verilog and System Verilog for programmable logic solutions.
Responsibilities
Custom Design Flow implementation
Semiconductor principles and transistor-level analysis
Characterization, performance, and power simulations
RTL coding and verification
Lint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA
Requirements
BS or MS in Electronics Engineering
BS or MS in Computer Engineering
BS or MS in Electrical Engineering
Nice to have: FPGA/CPLD design and integration
Nice to have: IP and Fullchip functional verification
Principal SRE to build, maintain and scale highly critical, security production services in a Google Cloud Platform environment
Compensation
$147,000.00 - $237,500.00/yr
Responsibilities
Architect Federal Resilience: Design, build, and operate secure, multi-cloud infrastructure (AWS/GCP) tailored for FedRAMP and DoD impact levels
Strategic Automation Leadership: Champion Infrastructure as Code (IaC) using Terraform and Monitoring as Code (MaC) to automate robust deployments and end-to-end observability across production environments
DevSecOps Orchestration: Integrate automated security and compliance capabilities into CI/CD pipelines (GitHub/GitLab/Jenkins)
Operational Excellence: Lead Root Cause Analysis (RCA) for critical incidents and participate in on-call rotations
Innovation & Mentorship: Foster a 'Community of Practice' for collective learning, integrating AI-driven development tools and mentoring teams on modern SRE practices and security tools
Requirements
BS/MS in Computer Science/Engineering or equivalent training, education, and experience in information / cyber security, computer systems, IT
Position:
Senior Engineer [Embedded C/Linux]
Job Description:
• Experience working with Embedded Linux Application programming.
• Strong knowledge for Linux OS, Inter Process Communication, and multi-threaded/multi-process application development.
• Programming skill:
o C à Advanced
o Scripting (Shell/Python) -> Intermediate
o C++ à Intermediate
• Familiarity working with development tools like GDB, Velgrin, SCA Tools, GIT, SVN, JIRA.
• Experience working with various build systems like, Jenkins, etc
• Experience working with different embedded platform like ARM/PowerPC processor and DSP based on Qualcomm, TI, NXP, NVIDIA, Intel processors
• Strong sense of ownership, passionate, fast learner, analytical mind set.
• * Ability to closely work with electrical team
• Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker.
Location:
IN-GJ-Ahmedabad, India-Ognaj (eInfochips)
Time Type:
Full time
Job Category:
Engineering Services