Sr. Software Test Engineer
Artech LLC · Austin, USSenior
Analyste d'exploitation H/F
Open 2 · Tours, France+1 more
IP Silicon Validation Engineer
Advanced Micro Devices, Inc · Markham, Canada+1 more
PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
Amazon · Austin, US+1 more · On-site · Full-time
+10K new in the last hour
Artech LLC · Posted Nov 4, 2026
Ability to perform manual testing and analysis to identify defects, verify Software requirements and prepare documents based on QMS and regulatory environment, provide leadership to Software Test Engineers.
Draft & execute Test Protocols Plan schedules for formal cycle testing Submit defects reports using defect tracking application and follow through on its resolution Prepare weekly test metrics and present report on a regular basis Participate in Defect Review Board and work with Software Quality Engineer to follow up on features & defects Bachelor's degree in Biomedical or Mechatronics or Computer Engineering, or a related field Open 2 · Posted Sep 16, 2026
Analyste d'exploitation H/F
Tours, France Orléans, Centre-Val de Loire, France Assurer le bon fonctionnement des applications métiers sur les environnements de test, recette et intégration Réaliser et suivre les déploiements applicatifs Créer, maintenir et optimiser les chaînes de traitement Gérer l’ordonnancement des traitements via des outils (Automator, Rundeck) Automatiser les tâches récurrentes via des scripts Bac+2 à Bac+5 en informatique (exploitation, systèmes, développement ou équivalent) Advanced Micro Devices, Inc · Posted Nov 3, 2026
IP Validation Design Engineer responsible for planning, validating, and debugging hardware IP for AMD SOC programs.
Markham, Ontario, Canada Vancouver, British Columbia, Canada Drive planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs Define, document, execute and report overall functional test plan and validation strategy for a set of AMD IPs Drive technical innovation to enhance AMD's capabilities in IP validation Debug IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs Engage in pre-silicon ‘shift left’ activities with cross-functional teams Bachelor’s or master’s degree majoring in EE, CS or related field Amazon · Posted Nov 4, 2026
Design and optimize physical design methodologies for ASICs in Amazon’s cloud-scale machine learning infrastructure.
Austin, Texas, United States Cupertino, California, United States USA, CA, Cupertino - 176,600.00 - 247,300.00 USD annually
USA, TX, Austin - 153,600.00 - 215,000.00 USD annually
Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes Drive optimizations in CAD flows/methodologies for PPA and TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability Fine tune cloud infrastructure to improve compute and storage utilization for physical design work Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies
Bachelor's degree in Electrical Engineering
Nice to have: Master's degree in Electrical or Communications Engineering
Nice to have: industry standard tools
Nice to have: scripting Python
Nice to have: scripting Perl Health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage) 401(k) matching Paid time off Parental leave
IP Silicon Validation EngineerAdvanced Micro Devices, Inc · Markham, Canada+1 more
PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine LearningAmazon · Austin, US+1 more