An experienced ASIC Package Engineer focused on advanced packaging development, process integration, and designing custom silicons for infrastructure/AI/ML and networking applications.
Locations (2)
Hsinchu, Taiwan, Taiwan
Taipei, Taiwan, Taiwan
Responsibilities
Perform package design for AI/ML and networking applications custom Si with single-chip/multi-chip and SiP/module packaging
Design feasibility studies and analyses to ensure good manufacturing at ODM
Lead development of disruptive advanced packaging technologies from concept to product, including test vehicle definition and building with ecosystem partners
Work with internal Si, architecture and system teams, and externally with engaged partners, ODM, design houses and OSAT companies
Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration
Lead the physical design implementation and strategy for high-performance silicon, managing end-to-end execution from RTL to GDSII and driving cross-functional collaboration.
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