- Full-time · Senior
- 8+ years
Lead analog design of high‑speed SERDES IP for advanced process nodes, driving architecture, performance, and integration with digital teams.
Responsibilities
- Review high‑speed SerDes standards and translate them into transceiver architectures
- Architect and design analog/mixed‑signal circuits including TX drivers, RX front‑ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and ADC/DAC blocks
- Collaborate with digital design teams on analog/digital co‑design, calibration loops, adaptation algorithms, and timing handoff
- Work directly with layout engineers to guide physical implementation, minimize parasitics, manage device stress and process variation
- Present simulation results, design trade‑offs, and architectural decisions in internal reviews, customer meetings, and industry panel discussions
Requirements
- MTech/MS with 8+ years or BTech/BS with 10+ years of hands‑on analog IC design experience in Electrical Engineering, Computer Engineering, or a related field
- Nice to have: high‑speed interleaved SAR ADCs