- Hyderabad, Telangana, India
- Senior
- 5+ years
Responsibilities
- Perform block- and IP-level verification to validate functionality, performance, and compliance with design requirements.
- Develop and execute verification plans based on architecture and design specifications, defining appropriate scenarios and closure criteria.
- Architect, implement, and maintain testbenches using SystemVerilog and UVM, including constrained-random stimulus, checkers, and assertions.
- Define and analyze functional coverage, identify gaps, and drive verification closure through coverage and regression analysis.
- Apply formal verification techniques to mixed-signal IP integration, including verification using real-number models (RNM).
Requirements
- B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics, Computer Engineering, VLSI, or a related field.
- Nice to have: wireless SoCs
- Nice to have: low-power IoT silicon
- Nice to have: MCU subsystems
- Nice to have: AMBA interconnect protocols