Referso Jobs

Participate in SOC full Chip DFT feature and architecture definition
Responsible for DFT specification generation and review
Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
Perform verification on all DFT structures
Generate DFT related timing constraints and work with PD team for timing closure

Requirements

BS in EE & CS
MS preferred
Nice to have: English language proficiency

Skills

ASIC DFT design ASIC DFT verification

DFT DV Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

Shanghai, Shanghai, China +1 more
On-site
Full-time · Senior
8+ years

Apply with RefersoAI Apply on careers page

The S3 DFT team owns AMD S3BU (Strategic Silicon Solution Business Unit) SOC DFT definition, Implementation, verification till final silicon bring up. The role involves designing APUs mainly for consoles and verifying debug logic to ensure it works on post-silicon.

Locations (2)

Shanghai, Shanghai, China
Beijing, Beijing, China

Responsibilities

Develop test plan according to the specification and review with Architect and Designer.
Develop test scenarios to verify the design and analyze the coverage.
Complete the verification task before TO.
Participate in ATE bring-up and debug the DFT patterns on ATE.

Requirements

Bachelor in EE
Master in EE
Bachelor in CS
Master in CS
Nice to have: VCS

Skills

ASIC design flow design verification

DFT DV Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

Shanghai, China +1 more
6+ years

Apply with RefersoAI Apply on careers page

Locations (2)

Shanghai, China
Beijing, China

Responsibilities

Develop test plan according to the specification and review with Architect and Designer.
Develop test scenarios to verify the design and analyze the coverage.
Complete the verification task before TO.
Participate in ATE bring-up and debug the DFT patterns on ATE.

Requirements

Bachelor
Master
Nice to have: simulation tool VCS
Nice to have: SystemVerilog
Nice to have: C

Skills

design verification debug skills ASIC design flow

Technical Program Manager, ASIC

ClifyX, INC · Posted Nov 5, 2026

Open

Full-time · Manager
10+ years

Apply with RefersoAI Apply on careers page

Lead cross‑functional and multi‑site teams to deliver ASICs for Client's infrastructure engineering organization.

Responsibilities

Manage cross‑functional infrastructure programs in a matrix organization covering a range of functional areas in Silicon Engineering, Platform Software, Hardware Systems, Sourcing & Operations and vendors.
Drive and manage ASIC development and their subsystems with vendors, from concept to production.
Provide hands‑on program management during all phases of silicon and firmware development from concept, design, development, fabrication, validation, qualification and production release phases.
Engage with stakeholders to define product development roadmaps.
Drive program execution to deliver high quality ASIC solutions.

Requirements

BS degree in Computer Science, Computer / Electrical Engineering or other technical field
Nice to have: RTL design experience with VHDL/Verilog/SystemVerilog
Nice to have: semiconductor technology and manufacturing processes
Nice to have: data center architecture and deployment
Nice to have: working with ODMs/vendors

Skills

ASIC development Program/Product Management

DFT Engineer

Advanced Micro Devices, Inc · Posted Nov 5, 2026

Open

Shanghai +1 more
8+ years

Apply with RefersoAI Apply on careers page

Design, implement, and verify DFT for AMD SOCs

Locations (2)

Shanghai
Beijing, China

Responsibilities

Participate in SOC full Chip DFT feature and architecture definition
Responsible for DFT specification generation and review
Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
Perform verification on all DFT structures
Generate DFT related timing constraints and work with PD team for timing closure

Requirements

BS in EE & CS
MS preferred
Nice to have: English language proficiency

Skills

ASIC DFT design ASIC verification

AI Accelerator Design Verification Engineer - Intern

RosaicLabs · Posted Oct 5, 2026

Open

Santa Clara, California, United States
On-site
Internship · Intern

Apply with RefersoAI Apply on careers page

The intern will verify the accelerator with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Responsibilities

Work with your mentor to develop verification plans for the accelerator
Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
Build tests, scoreboards, and reference models, and close functional and code coverage
Triage and root-cause failures with RTL designers, with mentorship from senior engineers
Participate in design and verification reviews and document your verification environment and results

Requirements

BS/MS in Electrical Engineering
Computer Engineering
Computer Science
Nice to have: parallel datapaths
Nice to have: SIMD / SIMT / vector processing

Skills

Digital design Verification computer microarchitecture digital logic and RTL design constrained-random verification

CPU RTL Microarchitecture/Design Engineer

RosaicLabs · Posted Sep 29, 2026

Open

Santa Clara, California, United States
Full-time

Apply with RefersoAI Apply on careers page

Design and implement CPU functional blocks based on microarchitecture specifications, develop, debug, and optimize RTL, analyze performance, timing, area, and power tradeoffs, work with verification and physical design engineers, participate in reviews and write documentation.

Responsibilities

Design and implement CPU functional blocks based on microarchitecture specifications
Develop, debug, and optimize RTL using SystemVerilog/Verilog
Analyze performance, timing, area, and power tradeoffs and propose improvements
Work with verification engineers to develop test plans and achieve functional coverage
Partner with physical design engineers on area, timing, and power goals

Requirements

Bachelor's or Master's degree (or near-term graduation) in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Skills

Verilog SystemVerilog RTL simulation Testbench-based debugging ASIC design flow RTL design

DFT DV Engineer

DFT DV Engineer

Locations (2)

Responsibilities

Requirements

Skills

DFT Engineer

Locations (2)

Responsibilities

Requirements

Skills

DFT DV Engineer

Locations (2)

Responsibilities

Requirements

Skills

DFT DV Engineer

Locations (2)

Responsibilities

Requirements

Skills

Technical Program Manager, ASIC

Responsibilities

Requirements

Skills

DFT Engineer

Locations (2)

Responsibilities

Requirements

Skills

AI Accelerator Design Verification Engineer - Intern

Responsibilities

Requirements

Skills

CPU RTL Microarchitecture/Design Engineer

Responsibilities

Requirements

Skills

Benefits

Benefits

ASIC design flow jobs

Locations (2)

Responsibilities

Requirements

Skills

Locations (2)

Responsibilities

Requirements

Skills

Locations (2)

Responsibilities

Requirements

Skills

Locations (2)

Responsibilities

Requirements

Skills

Responsibilities

Requirements

Skills

Locations (2)

Responsibilities

Requirements

Skills

Responsibilities

Requirements

Skills

Responsibilities

Requirements

Skills

Benefits

Benefits