Constrained Random verification jobs

Lead Engineer Design Verification

Quest Global · Posted Nov 13, 2026

Open

Windsor, Connecticut, United States +1 more
Senior
$172K–$172K per year
2+ years

Lead Engineer Design Verification

Quest Global · Posted Nov 13, 2026

Open

Windsor, Connecticut, United States +1 more
Senior
$172K–$172K per year
2+ years

Design Verification Engineer

Capgemini · Posted Nov 10, 2026

Open

Vila Nova de Gaia, Portugal
Hybrid
Full-time · Mid
4+ years

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Lead verification of complex digital IPs and SoCs in advanced semiconductor projects.

Responsibilities

Own verification of IPs and SoCs in prototype and SoC design environment
Establish functional and performance benchmarks
Lead the definition, execution, and continuous improvement of a robust design verification methodology and tools flow across different verification platforms
Perform IP and SoC design verification from the RTL level to emulation, resulting in fully functional and performant IPs/SoCs

Requirements

Degree in Electrical Engineering, Electronics, Computer Engineering, Microelectronics or a related field

Skills

SystemVerilog UVM/OVM Constrained Random Verification Coverage Driven Verification UVC components or sequences AHB/AXI PCIe/CXL

Verification Engineer, PCIE

NVIDIA · Posted Nov 6, 2026

Open

Bengaluru, Karnataka, India
Hybrid
Full-time · Senior
1+ years

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Senior Verification Engineer responsible for verifying PCI Express controller designs at ASIC and IP levels using UVM and related methodologies.

Compensation

With competitive salaries and a generous benefits package

Responsibilities

Verify ASIC design, architecture, golden models and micro-architecture of PCI Express controllers at IP/sub-system levels using UVM
Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology
Define verification scope, develop test plans, tests, and verification infrastructure
Collaborate with architects, designers, and pre and post silicon verification teams

Requirements

B.Tech.
M.Tech.
Nice to have: PCI Express Gen3
Nice to have: CXL
Nice to have: Perl

Skills

verification UVM VMM SystemVerilog Verilog PCI Express

Lead Engineer Design Verification

Lead Engineer Design Verification

Locations (2)

Compensation

Responsibilities

Requirements

Skills

Design Verification Engineer

Responsibilities

Requirements

Skills

Verification Engineer, PCIE

Compensation

Responsibilities

Requirements

Skills

Benefits

Benefits