Provide on-site professional technical support, primarily in North America, and develop innovative solutions to customer challenges in semiconductor manufacturing.
Compensation
Join Thermo Fisher Scientific and enjoy competitive pay, annual bonuses, healthcare, 401(k) plans, and various employee benefits such as: National medical, dental, and vision plans, Employee assistance and family support, Commuter benefits and tuition reimbursement, Generous paid time off and holiday, Paid parental leave, Accident, life insurance, and disability coverage, Retirement savings programs, Employee Stock Purchase Plan with discounts
Responsibilities
Provide on-site professional technical support, primarily in North America
Develop innovative solutions to customer challenges
Support tool acceptance and new technologies on location and in coordination with the product and service teams
Coordinate closely with internal product, engineering, marketing and account teams on product acceptance and development
Provide detailed technical feedback to the product teams on customer needs and product performance in the field
Requirements
Minimum of an undergraduate degree in Physics, Materials Science, Chemistry, or a related field; an advanced degree is preferred
Nice to have: Coding or scripting (C#, Python, MATLAB)
Field Applications Engineer responsible for enabling customers in the integration of TEM tools into semiconductor processes for development and production.
Responsibilities
Provide on-site professional technical support
Develop innovative solutions to customer challenges
Support tool acceptance and new technologies
Develop positive relationships with customers
Provide detailed technical feedback to product teams on customer needs and performance
Lead and drive innovation and technology development for high voltage power semiconductor device platforms, defining roadmaps, managing complex projects, and mentoring engineering teams.
Compensation
For this position, we offer a gross annual salary of approximately €120,000 to €160,000.
Responsibilities
Define technology roadmaps and long-term strategies
Identify emerging technologies, market trends, and competitive opportunities
Assess and influence alignment of device technologies with customer and application requirements
Generate intellectual property through patents and technical publications
Serve as the company's technical expert for critical device and technology challenges
Summer placement aimed at looking at the possible solution to reduce the deep sleep current and/or reduce the external component count in our future products. The project involves understanding the needs of reducing the deep sleep current and/or reducing the external component count in the analog blocks, coming up with the idea for the system level solution and coming up with the architecture for the blocks.
Responsibilities
work under the direction of a senior member of staff
complete and document the tasks so that the designs can be reused in future products
design blocks and prove them in a test-chip in a deep sub-micron process
Senior Engineer role focused on reliability test flow development, DPM reduction, and root cause analysis for HBM products, utilizing AI and machine learning to enhance product qualification workflows.
Responsibilities
Define and develop reliability stress, test flows and test plans to cover all Product Reliability aspects.
Work closely with Global Quality team to define qualification plan, review and manage the qualification execution progress, and drive for qualification gating issue resolution.
Drive down and achieving Extrinsic Reliability and Intrinsic Reliability through Optimized Manufacturing Test Flows and Test Strategy.
Debug and identify root cause and failures in reliability tests by electric failure analysis(EFA) and Physical Failure Analysis (PFA).
Provide recommendation to fab teams for new process conversions to reduce cost and increase yields.
Requirements
Bachelor’s or Master’s degree in Electrical and Electronics Engineering or a related field
Design and develop high-speed IO circuits for next-generation memory interface PHY IPs including DDR, HBM, and UCIe in advanced CMOS, FinFET, and GAA process nodes.
Responsibilities
Design and develop high-speed IO circuits for next-generation memory interface PHY IPs
Execute circuit design tasks from architecture through layout, simulation, and verification with a focus on performance, power, and area optimization
Analyze and solve complex analog design challenges in advanced technology nodes
Collaborate with global cross-functional teams to deliver integrated PHY solutions
Apply ESD and reliability principles to ensure robust circuit design
Requirements
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field
Nice to have: knowledge of JEDEC memory interface standards (DDR, HBM, LPDDR)
Nice to have: familiarity with signal integrity and power integrity concepts
Senior Engineer responsible for reliability test flow development, test planning, DPM reduction, root cause analysis, process conversion recommendations, risk management, project management, AI strategy for reliability, and applied machine learning for reliability datasets.
Responsibilities
Define and develop reliability stress, test flows and test plans
Work closely with Global Quality team to define qualification plan and manage execution
Drive down and achieve Extrinsic and Intrinsic Reliability through optimized manufacturing test flows
Debug and identify root cause and failures in reliability tests by EFA and PFA
Provide recommendations to fab teams for new process conversions
Requirements
Bachelor's or Master's degree in Electrical and Electronics Engineering or a related field
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