- Broomfield, Colorado, United States
- $122K–$195K per year
- 8+ years
Lead and execute synthesis, static timing analysis, formal verification, and low‑power implementation activities for mixed‑signal ASIC blocks, manage IP release and drive automation of implementation workflows.
Compensation
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
Responsibilities
- Execute synthesis and run static checks for digital/mixed‑signal blocks
- Create, validate, and maintain timing constraints and perform STA
- Run formal verification and logical equivalence checking
- Generate and implement timing/functional ECOs for timing closure
- Serve as final gatekeeper for IP deployment and release validation
Requirements
- BS in Electrical Engineering, Computer Engineering, or a related field
- MS in Electrical Engineering, Computer Engineering, or a related field