- San Jose, California, United States
- On-site
- Full-time · Senior
- $122K–$195K per year
- 10+ years
The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up, supporting various phases of SoC DFT-related activities for Broadcom APD’s designs.
Compensation
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
Responsibilities
- Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
Requirements
- Bachelor's degree in Electrical Engineering
- Master's degree in Electrical Engineering
- Bachelor's degree in Computer Engineering
- Master's degree in Computer Engineering
- Nice to have: Experience working on ATE