Lead RTL design methodology and static signoff flows for Ericsson’s 5G and 6G ASIC and FPGA programs.
Locations (4)
Austin, Texas, United States
Stockholm, Stockholm County, Sweden
Lund, Sweden
India, Madhya Pradesh, India
Compensation
The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.
Responsibilities
Own RTL design methodology: Define coding guidelines, lint rule sets, waiver policy, and signoff criteria for IP, subsystem, and SoC teams.
Lead lint, CDC, and RDC signoff: Architect structural, formal, and hybrid CDC and RDC flows with progressive goals and hierarchical signoff using abstract models and clock/reset constraints.
Build vendor-agnostic flows: Deliver single-command static signoff in OneRun with standard project templates and Jenkins CI quality gates.
Drive RTL reuse and automation: Architect configurable RTL frameworks and standard interfaces for multi-program IP reuse.
Apply AI to RTL engineering: Use and improve AI tools such as ChipAgents and Kiro for RTL development, documentation, code conversion, and lint and CDC triage.
Requirements
Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field—or equivalent practical experience.
