Technical staff position leads and/or develops and executes exceptionally complex technology and engineering projects and research and development of new technologies.
Compensation
Salary: $163,000.00 - $224,000.00
Responsibilities
Develop and implement concepts for a wide range of significantly complex product issues and engineering solutions
Technical lead and/or execute engineering projects and spearhead research and development of new technologies
Problem identification and troubleshooting a wide range of significantly complex engineering problems
Specify and/or perform engineering analysis of significant complex scope
Interface with internal and external customers regarding significantly complex electrical issues to address customers High Value Problems (HVP)
As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products.
Responsibilities
Drive PPAC assessment and technology pathfinding for System-Technology Co-Optimization (STCO) and heterogeneous integration.
Evaluate and develop 2.5D/3D chiplet integration solutions, including SoIC, CoWoS, WoW, hybrid bonding, interposer, and RDL technologies.
Perform custom DRAM and 3D SRAM integration evaluation and pathfinding for advanced product development.
Develop and support test-chip design, mask layout, design flows, and PDK enablement for advanced silicon and packaging technologies.
Perform layout and design analysis for advanced technology benchmarking, DFM, and product issue debugging.
Requirements
Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
Senior engineer responsible for developing, qualifying, and delivering production-quality EM/IR reliability collateral and methodologies across advanced process technologies for Intel’s PDK Reliability Verification / EMIR team.
Locations (3)
Phoenix, Arizona, United States
Folsom, California, United States
Santa Clara, California, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
Responsibilities
Develop, qualify, and maintain PDK EMIR collateral, documentation, and technology-specific configurations.
Own or contribute to PDK and Reliability Technology Kit (RTK) development, qualification, QA, and release readiness.
Develop and maintain test structures and automated validation for EM/IR collateral, including validation and cross-tool correlation.
Sell analog and mixed-signal EDA tools to semiconductor companies, lead technical pre‑sales engagements, identify new sales opportunities, collaborate with engineering and product teams, and maintain customer relationships.
Compensation
Base Salary Range: $144000 - $216000
The base salary range for this role is across the U.S.
Responsibilities
Sell analog and mixed-signal EDA tools to semiconductor companies by understanding their design challenges, circuit architectures, and methodology gaps, then mapping those to Synopsys solutions
Lead technical pre‑sales engagements including product demonstrations, proof‑of‑concept setups, and custom workflow proposals tailored to customer design environments
Identify new sales opportunities by staying close to customer roadmaps, understanding where their next‑generation designs (data converters, PLLs, SerDes, power management) will push their current tools to the limit
Collaborate with engineering, product marketing, and R&D teams to shape solutions that are not just technically sound but actually deployable in customer workflows
Build and maintain relationships with design teams, CAD managers, and engineering leadership at key accounts, becoming the technical voice they trust when evaluating tooling decisions
Heterogeneous Integration Physical Design EngineerQualcomm · Hsinchu City, Taiwan
Sales Account Management, Sr StaffSynopsys · US