Provide critical technology support for the design and development of advanced HBM DRAM products, serving as a bridge between internal design teams, foundries, and technology development groups.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $150,000.00 - $308,000.00 a year
Responsibilities
Foundry Interface and Technology Alignment
Circuit Simulation and Analysis
Test-Chip and Silicon Validation
PDK and Design Enablement
AI-Enabled Productivity and Efficiency Improvement
Requirements
BS or MS or PhD or equivalent experience in Electrical Engineering, Computer Engineering, or related field
Nice to have: TSV technologies
Nice to have: Advanced packaging
Nice to have: Reliability modeling and aging simulations
Provide critical technology support for the design and development of advanced HBM DRAM products, serving as a bridge between internal design teams, foundries, and technology development groups.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $181,000.00 - $308,000.00 a year
Responsibilities
Foundry Interface and Technology Alignment
Circuit Simulation and Analysis
Test-Chip and Silicon Validation
PDK and Design Enablement
AI-Enabled Productivity and Efficiency Improvement
Requirements
BS, MS, or PhD or equivalent experience in Electrical Engineering, Computer Engineering, or related field
Nice to have: TSV technologies
Nice to have: Advanced packaging
Nice to have: Reliability modeling and aging simulations
Provide critical technology support for the design and development of advanced HBM DRAM products, bridging internal design teams, foundries, and technology development groups.
Compensation
$181,000.00 - $415,000.00 a year
Responsibilities
Provide critical technology support for the design and development of advanced HBM DRAM products
Serve as a bridge between internal design teams, foundries, and technology development groups
Translate advanced process capabilities into scalable, high‑performance architectures
Support the design and deployment of AI‑enabled solutions that improve efficiency and decision‑making
Provide critical technology support for the design and development of advanced HBM DRAM products, serving as a bridge between internal design teams, foundries, and technology development groups.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $181,000.00 - $308,000.00 a year
Responsibilities
Foundry Interface and Technology Alignment
Circuit Simulation and Analysis
Test-Chip and Silicon Validation
PDK and Design Enablement
AI-Enabled Productivity and Efficiency Improvement
Requirements
BS, MS, or PhD or equivalent experience in Electrical Engineering, Computer Engineering, or related field
Nice to have: TSV technologies
Nice to have: Advanced packaging
Nice to have: Reliability modeling and aging simulations
Lead design and technology support for advanced HBM DRAM products, bridging internal teams, foundries, and technology groups to translate process capabilities into scalable, high‑performance architectures.
Compensation
$150,000.00 - $308,000.00 a year
Responsibilities
Provide critical technology support for design and development of advanced HBM DRAM products
Serve as a bridge between internal design teams, foundries, and technology development groups
Translate advanced process capabilities into scalable, high‑performance architectures
Support design and deployment of AI‑enabled solutions that improve efficiency and decision‑making
Provide critical technology support for the design and development of advanced HBM DRAM products, bridging internal design teams, foundries, and technology development groups.
Compensation
$181,000.00 - $415,000.00 a year
Responsibilities
Provide critical technology support for the design and development of advanced HBM DRAM products
Serve as a bridge between internal design teams, foundries, and technology development groups
Translate advanced process capabilities into scalable, high‑performance architectures
Support the design and deployment of AI‑enabled solutions that improve efficiency and decision‑making
Leverage the understanding of the phases of silicon development to flesh out the architecture and lead development and deployment of the overall CI2 design environment as a coherent system composed of first-party and third-party tools, industry-standard and Google-specific APIs/data formats and the scalable design flows.
Collaborate with technical leaders across CI2 sites to identify opportunities for evolutionary and revolutionary tooling and methodology changes to enable convergence on a shared design environment.
Engage with other Alphabet teams, DeepMind, and Core teams to ensure CI2 stays at the forefront of advanced silicon development.
Ensure developed technologies optimize for project iteration speed while achieving the planned power, performance, cost, and quality metrics.
Partner with other members of the tools and methodologies team to apply procedural and AI-first approaches to improve efficiency.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
Responsibilities
Block level PnR, floor-planning, clock, power planning and distribution
Static Timing closure using commercial tools
Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )
Help build the tools, flows and automation our physical design teams use to tape out high-performance ASICs and mixed-signal chips.
Compensation
$154,000—$175,000 USD
Responsibilities
Develop, maintain and extend our physical design flows from synthesis through signoff (place-and-route, CTS, STA, power integrity, DRC/LVS), mostly in Python and TCL.
Use AI and LLM-based tools to automate flow tasks such as report triage, debug, constraint checking, DRC/LVS analysis, run monitoring and QoR prediction.
Research and prototype new flow capabilities, EDA tool features and methodologies, then turn the successful ones into production flows.
Build tools for regression testing, QoR tracking and dashboards so flow changes are measurable and safe.
Support the implementation teams by debugging flow problems, reproducing tool issues and working with EDA vendors on fixes.
Lead the interface between foundry partners and Micron design teams to advance HBM DRAM technology.
Compensation
$150,000.00 - $308,000.00 a year
Responsibilities
Act as the primary technical interface between foundry partners and Micron design organizations
Drive closure of design-process gaps through collaborative engagement with foundry process teams
Influence foundry roadmaps related to TSV, BEOL, reliability, and design enablement
Define technology requirements for future HBM and custom memory products
Perform HSPICE simulations for technology evaluation and design optimization
Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
Nice to have: Experience with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries
Nice to have: Experience with memory products including DRAM, HBM, or SRAM
Nice to have: Knowledge of TSV technologies, Advanced packaging, Reliability modeling and aging simulations, Advanced BEOL technologies, PDK development and validation
Nice to have: Experience leading technology pathfinding and node selection activities
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